DP83849IF Datasheet, PDF (47/108 Pages) National Semiconductor (TI) – PHYTER® DUAL Industrial Temperature with Fiber Support (FX) an Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver

5.8.3 TDR Cable Diagnostics
The DP83849IF implements a Time Domain Reflectometry
(TDR) method of cable length measurement and evalua-
tion which can be used to evaluate a connected twisted
pair cable. The TDR implementation involves sending a
pulse out on either the Transmit or Receive conductor pair
and observing the results on either pair. By observing the
types and strength of reflections on each pair, software can
determine the following:
— Cable short
— Cable open
— Distance to fault
— Identify which pair has a fault
— Pair skew
This is especially useful for eliminating the transmitted
pulse, but also may be used to look for multiple reflections.
5.8.3.3 TDR Control Interface
The TDR Control interface is implemented in the Link Diag-
nostics Registers - Page 2 through TDR Control
(TDR_CTRL), address 16h and TDR Window (TDR_WIN),
address 17h. The following basic controls are:
— TDR Enable: Enable bit 15 of TDR_CTRL (16h) to allow
the TDR function. This bypasses normal operation and
gives control of the CD10 and CD100 block to the TDR
function.
— TDR Send Pulse: Enable bit 11 of TDR_CTRL (16h) to
send the TDR pulse and starts the TDR Monitor.
The TDR cable diagnostics works best in certain condi-
tions. For example, an unterminated cable provides a
good reflection for measuring cable length, while a cable
with an ideal termination to an unpowered partner may pro-
vide no reflection at all.
5.8.3.1 TDR Pulse Generator
The TDR implementation can send two types of TDR
pulses. The first option is to send 50ns or 100ns link
pulses from the 10Mb Common Driver. The second option
is to send pulses from the 100Mb Common Driver in 8ns
increments up to 56ns in width. The 100Mb pulses will
alternate between positive and negative pulses. The
shorter pulses provide better ability to measure short cable
lengths, especially since they will limit overlap between the
transmitted pulse and a reflected pulse. The longer pulses
may provide better measurements of long cable lengths.
In addition, if the pulse width is programmed to 0, no pulse
will be sent, but monitor circuit will still be activated. This
allows sampling of background data to provide a baseline
for analysis.
5.8.3.2 TDR Pulse Monitor
The TDR function monitors data from the Analog to Digital
Converter (ADC) to detect both peak values and values
above a programmable threshold. It can be programmed
to detect maximum or minimum values. In addition, it
records the time, in 8ns intervals, at which the peak or
threshold value first occurs.
The TDR monitor implements a timer that starts when the
pulse is transmitted. A window may be enabled to qualify
incoming data to look for response only in a desired range.
The following Transmit mode controls are available:
— Transmit Mode: Enables use of 10Mb Link pulses from
the 10Mb Common Driver or data pulses from the 100Mb
Common Driver by enabling TDR 100Mb, bit 14 of
TDR_CRTL (16h).
— Transmit Pulse Width: Bits [10:8] of TDR_CTRL (16h)
allows sending of 0 to 7 clock width pulses. Actual puls-
es are dependent on the transmit mode. If Pulse Width
is set to 0, then no pulse will be sent.
— Transmit Channel Select: The transmitter can send
pulses down either the transmit pair or the receive pair
by enabling bit 13 of TDR_CTRL (16h). Default value is
to select the transmit pair.
The following Receive mode controls are available:
— Min/Max Mode Select: Bit 7 of TDR_CTRL (16h) con-
trols the TDR Monitor operation. In default mode, the
monitor will detect maximum (positive) values. In Min
mode, the monitor will detect minimum (negative) val-
ues.
— Receive Channel Select: The receiver can monitor ei-
ther the transmit pair or the receive pair by enabling bit
12 of TDR_CTRL (16h). Default value is to select the
transmit pair.
— Receive Window: The receiver can monitor receive
data within a programmable window using the TDR Win-
dow Register (TDR_WIN), address 17h. The window is
controlled by two register values: TDR Start Window, bits
[15:8] of TDR_WIN (17h) and TDR Stop Window, bits
[7:0] of TDR_WIN (17h). The TDR Start Window indi-
cates the first clock to start sampling. The TDR Stop
Window indicates the last clock to sample. By default,
the full window is enabled, with Start set to 0 and Stop
set to 255. The window range is in 8ns clock increments,
so the maximum window size is 2048ns.
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