DP83261 Datasheet, PDF (45/132 Pages) National Semiconductor (TI) – BMAC Device (FDDI Media Access Controller)

6 0 Control Information (Continued)
Counter Overflow Mask Register (COMR)
The Counter Overflow Mask Register (COMR) is used to mask bits from the Counter Overflow Latch Register (COLR) If a bit in
Register COMR is set to One the corresponding bit in Register COLR will be applied to the Interrupt Condition Register which
can then be used to generate an interrupt
All bits in this register are set to Zero upon reset
ACCESS RULES
Address
Read
Write
1Dh
Always
Always
REGISTER BITS
D7
D6
D5
D4
D3
D2
D1
D0
RES TKRCVD FRTRX FRNCOP FRCOP FRLST FREI FRRCV
Bit Symbol
Description
D0 FRRCV
Frame Received Counter Overflow Mask This bit is used to mask COLR FRRCV
D1 FREI
Error Isolated Counter Overflow Mask This bit is used to mask COLR FREI
D2 FRLST
Lost Frame Counter Overflow Mask This bit is used to mask COLR FRLST
D3 FRCOP Frame Copied Counter Overflow Mask This bit is used to mask COLR FRCOP
D4 FRNCOP Frame Not Copied Counter Overflow Mask This bit is used to mask COLR FRNCOP
D5 FRTRX
Frame Transmitted Counter Overflow Mask This bit is used to mask COLR FRTRX
D6 TKRCVD Token Received Counter Overflow Mask This bit is used to mask COLR TKRCVD
D7 RES
Reserved
45