USBN9604 Datasheet, PDF (42/60 Pages) National Semiconductor (TI) – Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support

7.0 Register Set (Continued)
AEH
Automatic Error Handling. This bit has two different meanings, depending on the current transaction mode:
q _{Non-Isochronous mode}
This mode is used for bulk, interrupt and control transfers. Setting AEH in this mode enables automatic handling of
packets containing CRC or bit-stuffing errors.
If this bit is set during transmit operations, the device automatically reloads the FIFO and reschedules the packet to
which the host did not return an ACK. If this bit is cleared, automatic error handling ceases.
If this bit is set during receive operations, a packet received with an error (as specified in the DERR bit description in
the DMAEV register) is automatically flushed from the FIFO being used so that the packet can be received again. If
this bit is cleared, automatic error handling ceases.
q _{Isochronous mode}
Setting this bit allows the device to ignore packets received with errors (as specified in the DERR bit description in
the DMAMSK register).
If this bit is set during receive operations, the device is automatically flushed and resets the receive FIFO to receive
the next packet. The erroneous packet is ignored and not transferred via DMA. If this bit is cleared, automatic error
handling ceases.
7.2.12 Wake-Up Register (WKUP)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FHT
HOS WKMODE Reserved ENUC ENUSB PNDUC PNDUSB
0
0
0
-
1
1
1
1
w/r0
w/r
w/r
-
w/r
w/r
CoW
CoW
PNDUSB
Pending USB Wake-Up. This bit indicates that the device has been woken up by a USB activity. It also signals a pending
wake-up interrupt request. The PNDUSB bit must be cleared by the host by writing a 0 to this location. A hardware reset
sets this bit.
PNDUC
Pending Microcontroller Wake-Up. This bit indicates that the device has been woken up by a microcontroller access. It
also signals a pending wake-up interrupt request. The PNDUC bit must be cleared by the host by writing a 0 to this loca-
tion. A hardware reset sets this bit.
ENUSB
Enable USB. When set to 1, this bit enables the device to wake up upon detection of USB activity.
ENUC
Enable Microcontroller. When set to 1, this bit enables the device to wake up when the microcontroller accesses the device.
WKMODE
Wake-Up Mode. This bit selects the interval after which the device generates a wake-up interrupt (if enabled) when a valid
wake-up event occurs, as follows:
0 Generate wake-up interrupt immediately
1 Generate wake-up interrupt after a wake-up delay
HOS
Halt On Suspend. When this bit is set, the device enters Halt mode as soon as it is set to Suspend state. Writing a 1 to this
location while the node is already in Suspend state is ignored.
FHT
Force Halt. When the node is not attached (NAT in the MCNTRL register is set to 0), setting this bit forces the node into Halt
mode. When the node is attached (NAT is set to 1), writing a 1 to this location is ignored.
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