CR16MES5 Datasheet, PDF (40/99 Pages) National Semiconductor (TI) – Family of CompactRISC 16-Bit Microcontrollers

12.0 Multi-Input Wake-Up
The Multi-Input Wake-Up (MIWU) module monitors its eight
input channels for a software-selectable trigger condition.
Upon detection of a trigger condition, the module generates
either a wake-up request or an interrupt request. A wake-up
request can be used by the power management unit to exit
the Halt, Idle, or Power Save mode and return to the active
mode. An interrupt request generates an interrupt to the CPU
(interrupt IRQ2), allowing interrupt processing in response to
external events.
The wake-up event only activates the clocks and CPU, but
does not by itself initiate execution of any code. It is the inter-
rupt request associated with the MIWU that gets the CPU to
start executing code by jumping to the proper interrupt rou-
tine. Therefore, setting up the MIWU interrupt handler is es-
sential for any wake-up operation.
Figure8 is a block diagram showing the internal operation of
the Multi-Input Wake-Up module.
The input pins for the Multi-Input Wake-Up channels are
named WUI0 through WUI7. These pins are alternate func-
tions of I/O pins in Port I and Port L. The first Multi-Input
Wake-Up channel is software-selectable between the WUI0
input pin and the T0OUT signal from the Timing and Watch-
dog (TWM) module, which can be used to wake up the de-
vice after a programmed time interval. The WKCTL register
controls this selection. The remaining seven channels al-
ways use input pins WUI1 through WUI7.
Each input can be configured to trigger on rising or falling
edges, as determined by the setting in the WKEDG register.
Each trigger event is latched into the WKPND register. If a
trigger event is enabled by its respective bit in the WNENA
register, an active wake-up/interrupt signal is generated. The
software can determine which channel has generated the ac-
tive signal by reading the WKPND register.
The Multi-Input Wake-Up module is active at all times, includ-
ing the Halt mode. All device clocks are stopped in this mode.
Therefore, detecting an external trigger condition and the
subsequent setting of the pending flag are not synchronous
to the system clock.
12.1 WAKE-UP EDGE DETECTION REGISTER
(WKEDG)
The Wake-Up Edge Detection (WKEDG) register is a byte-
wide read/write register that controls the edge sensitivity of
the Multi-Input Wake-Up pins. Register bits 0 through 7 con-
trol input pins WUI0 through WUI7, respectively. A bit cleared
to 0 configures the corresponding input to trigger on a rising
edge (a low-to-high transition). A bit set to 1 configures the
corresponding input to trigger on a falling edge (a high-to-low
transition).
This register is cleared upon reset, which configures all eight
inputs to be triggered on rising edges.
The register format is shown below.
7
6
5
4
3
2
1
0
WKED7 WKED6 WKED5 WKED4 WKED3 WKED2 WKED1 WKED0
12.2 WAKE-UP ENABLE REGISTER (WKENA)
The Wake-Up Enable (WKENA) register is a byte-wide read/
write register that enables or disables each of the Multi-Input
Wake-Up channels. Register bits 0 through 7 control chan-
nels WUI0 through WUI7, respectively. A bit cleared to 0 dis-
ables the wake-up/interrupt function and a bit set to 1
enables the function.
This register is cleared upon reset, which disables all eight
wake-up/interrupt channels.
WKCTRL
7 _{..........................} 0
WUI0
T0OUT
WUI0
Peripheral Bus
7 ^{..........................} 0
WKENA
0
WUI7
7
WKEDG
WKPND
Figure 8. Multi-Input Wake-Up Module Block Diagram
EXINT to ICU and
Wake-up Signal
To Power Mgt
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