SCAN50C400A Datasheet, PDF (4/30 Pages) National Semiconductor (TI) – 1.25/2.5/5.0 Gbps Quad Multi-Rate Backplane Transceiver

Pin Descriptions
Pin Name
Ball
Number
I/O, Type
HIGH-SPEED DIFFERENTIAL I/O
HT1+
L22
O, CML
HT1−
L21
HT2+
HT2−
J22
O, CML
J21
HT3+
HT3−
G22
O, CML
G21
HT4+
HT4−
E22
O, CML
E21
HR1+
HR1−
N22
I, CML
N21
HR2+
HR2−
R22
I, CML
R21
HR3+
HR3−
U22
I, CML
U21
HR4+
HR4−
W22
W21
I, CML
REFERENCE CLOCK
SCLK+
A16
SCLK−
B16
I, HSTL
TRANSMIT INPUT DATA
T1_1+
K3
I, LVDS
T1_1−
K4
T1_2+
J3
T1_2−
J4
T1_3+
H1
T1_3−
H2
T1_4+
G1
T1_4−
G2
T1_5+
F3
I, LVDS
T1_5−
F4
T1_6+
E3
T1_6−
E4
T1_7+
D1
T1_7−
D2
T1_8+
C1
T1_8−
C2
T1_CLK+ K1
I, LVDS
T1_CLK− K2
Description
Inverting and non-inverting high-speed CML differential outputs of the serializer,
channel 1. Data is sourced from T1_1±, T1_2±, T1_3± and T1_4±. On-chip 50Ω termination
resistors connect from HT1+ and HT1− to V_DDHS.
Inverting and non-inverting high-speed CML differential outputs of the serializer,
channel 2. Data is sourced from T1_5±, T1_6±, T1_7± and T1_8±. On-chip 50Ω termination
resistors connect from HT2+ and HT2− to V_DDHS.
Inverting and non-inverting high-speed CML differential outputs of the serializer,
channel 3. Data is sourced from T2_1±, T2_2±, T2_3± and T2_4±. On-chip 50Ω termination
resistors connect from HT3+ and HT3− to V_DDHS.
Inverting and non-inverting high-speed CML differential outputs of the serializer,
channel 4. Data is sourced from T2_5±, T2_6±, T2_7± and T2_8±. On-chip 50Ω termination
resistors connect from HT4+ and HT4− to V_DDHS.
Inverting and non-inverting high-speed differential inputs of the deserializer, channel 1. Data is
de-serialized and output at R1_1±, R1_2±, R1_3± and R1_4±. On-chip 50Ω termination
resistors connect from HR1+ and HR1− to an internal bias.
Inverting and non-inverting high-speed differential inputs of the deserializer, channel 2. Data is
de-serialized and output at R1_5±, R1_6±, R1_7± and R1_8±. On-chip 50Ω termination
resistors connect from HR2+ and HR2− to an internal bias.
Inverting and non-inverting high-speed differential inputs of the deserializer, channel 3. Data is
de-serialized and output at R2_1±, R2_2±, R2_3± and R2_4±. On-chip 50Ω termination
resistors connect from HR3+ and HR3− to an internal bias.
Inverting and non-inverting high-speed differential inputs of the deserializer, channel 4. Data is
de-serialized and output at R2_5±, R2_6±, R2_7± and R2_8±. On-chip 50Ω termination
resistors connect from HR4+ and HR4− to an internal bias.
Inverting and non-inverting differential reference clock to the PLL for generating internal high-
speed clocks. A low jitter 125 MHz ±100 ppm clock should be connected to SCLK±. All four
serializers and deserializers are frequency-locked to SCLK±. A 50 Ω termination to Ground is
present on each input pin.
Differential transmit input data for channel 1. An on-chip 100 Ω resistor is connected between
each pair of complimentary inputs.
T1[1–4]± are synchronous to clock T1_CLK±. Data at T1[1–4]± are serialized and output at
HT1±. T1_1 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of
T1_CLK±.
Differential transmit input data for channel 2. An on-chip 100 Ω resistor is connected between
each pair of complimentary inputs.
T1[5–8]± are synchronous to clock T1_CLK±. Data at T1[5–8]± are serialized and output at
HT2±. T1_5 is shifted out first, see Figure 2. Data is strobed on both rising and falling edges of
T1_CLK±.
Differential 625 MHz transmit nibble clock for channels 1 and 2. Data at T1[1–4]± and T1[5–8]
± are strobed-in at both rising and falling edges of T1_CLK±, forming an 8-bit input data bus at
1.25 Gbps. T1_CLK± should be frequency-locked to reference clock SCLK±. An on-chip 100
Ω resistor is connected between each pair of complimentary inputs.
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