OPA320 Datasheet, PDF (4/37 Pages) Texas Instruments – Precision, 20MHz, 0.9pA, Low-Noise, RRIO, CMOS Operational Amplifier with Shutdown

OPA320, OPA2320
OPA320S, OPA2320S
SBOS513E – AUGUST 2010 – REVISED JUNE 2013
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ELECTRICAL CHARACTERISTICS: V_S = +1.8V to +5.5V or ±0.9V to ±2.75V (continued)
Boldface limits apply over the specified temperature range, T_A = –40°C to +125°C.
At T_A = +25°C, R_L = 10kΩ connected to V_S/2, V_CM = V_S/2, V_OUT = V_S/2, and SHDN x = V_S+, unless otherwise noted.
OPA320, OPA320S, OPA2320, OPA2320S
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
OUTPUT
Voltage output swing from
both rails
Over temperature
Short-circuit current
Capacitive load drive
Open-loop output resistance
SHUTDOWN ⁽³⁾
V_O
R_L = 10kΩ
R_L = 2kΩ
R_L = 10kΩ
R_L = 2kΩ
I_SC
V_S = 5.5V
C_L
R_O
I_O = 0mA, f = 1MHz
10
20
25
35
30
45
±65
See Typical Characteristics
90
All amplifiers disabled, SHDN = V–
0.1
0.5
Quiescent current per amplifier
High-level input voltage
Low-level input voltage
Amplifier enable time⁽⁴⁾
I_QSD OPA2320S only, SHDN A = V_S–, SHDN B = V_S+
1.6
OPA2320S only, SHDN A = V_S+, SHDN B = V_S–
1.6
V_IH Amplifier enabled, V_S– + 0.7 [(V_S+) + |V_S–|]
0.7 × V_S+
5.5
V_IL Amplifier disabled, V_S– + 0.3 [(V_S+) + |V_S–|]
t_ON
G = 1, V_OUT = 0.1 × V_S/2, full shutdown⁽⁵⁾
OPA2320S only, partial shutdown⁽⁵⁾
0.3 × V_S+
20
6
Amplifier disable time⁽⁴⁾
t_OFF
SHDN pin input bias current (per pin)
POWER SUPPLY
G = 1, V_OUT = 0.1 × V_S/2
V_IH = 5V
V_IL = 0V
3
0.13
0.04
Specified voltage range
Quiescent current per amplifier
OPA320, OPA320S
Over temperature
OPA2320, OPA2320S
Over temperature
Power-on time
TEMPERATURE
V_S
I_Q
I_O = 0mA, V_S = +5.5V
I_O = 0mA, V_S = +5.5V
I_O = 0mA, V_S = +5.5V
I_O = 0mA, V_S = +5.5V
V+ = 0V to 5V, to 90% I_Q level
1.8
5.5
1.5
1.75
1.85
1.45
1.6
1.7
28
Specified range
–40
+125
Operating range
–40
+150
UNIT
mV
mV
mV
mV
mA
Ω
μA
mA
mA
V
V
μs
μs
μA
μA
V
mA
mA
mA
mA
μs
°C
°C
(3) Specified by design and characterization; not production tested.
(4) Disable time (t_OFF) and enable time (t_ON) are defined as the time between the 50% point of the signal applied to the SHDN pin and the
point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(5) Full shutdown refers to the dual OPA2320S having both A and B channels disabled (SHDN A = SHDN B = V_S–). For partial shutdown,
only one SHDN pin is exercised; in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
4
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