LP3879 Datasheet, PDF (4/11 Pages) National Semiconductor (TI) – Micropower 800mA Low Noise Ceramic Stable Voltage Regulator for Low Voltage Applications

Electrical Characteristics (Continued)
Limits in standard typeface are for T_J = 25˚C, and limits in boldface type apply over the temperature range of -40˚C to 125˚C.
Limits are guaranteed through design, testing, or correlation. The limits are used to calculate National’s Average Outgoing
Quality Level (AOQL). Unless otherwise specified: V_IN = 3.0V, V_OUT = 1V, I_L = 1 mA, C_OUT = 10 µF, C_IN = 4.7 µF, V_S/D = 2V,
C_BYPASS = 10 nF.
Symbol
Parameter
Conditions
Min
(Note 6)
Typical
(Note 7)
Max
(Note 6)
Units
SHUTDOWN INPUT
V_S/D
I_S/D
S/D Input Voltage
S/D Input Current
V_H = Output ON
V_L = Output OFF
I_IN ≤ 10 µA
V_OUT ≤ 10 mV
I_IN ≤ 50 µA
V_S/D = 0
V_S/D = 5V
1.4
1.6
0.1
0.50
V
0.6
0.02
−1
µA
5
15
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the
device outside of its rated operating conditions.
Note 2: ESD testing was performed using Human Body Model, a 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 3: The maximum allowable power dissipation is a function of the maximum junction temperature, T_J(MAX), the junction-to-ambient thermal resistance, θ_J−A,
and the ambient temperature, T_A. The maximum allowable power dissipation at any ambient temperature is calculated using:
The value of θ_J−A for the LLP (SD) and PSOP (MRA) packages are specifically dependent on PCB trace area, trace material, and the number of layers and thermal
vias. If a four layer board is used with maximum vias from the IC center to the heat dissipating copper layers, values of θ_J−A which can be obtained are approximately
60˚C/W for the PSOP-8 and 40˚C/W for the LLP-8 package. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown.
Note 4: If used in a dual-supply system where the regulator load is returned to a negative supply, the LP3879 output must be diode-clamped to ground.
Note 5: The output PNP structure contains a diode between the V_IN and V_OUT terminals that is normally reverse-biased. Forcing the output above the input will turn
on this diode and may induce a latch-up mode which can damage the part (see Application Hints).
Note 6: Limits are guaranteed through testing, statistical correlation, or design.
Note 7: Typical numbers reperesent the most likely norm for 25˚C operation.
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