LM3668_08 Datasheet, PDF (4/18 Pages) National Semiconductor (TI) – 1A, High Efficiency Dual Mode Single Inductor Buck-Boost DC/DC Converter

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PV_IN, V_DD Pin, SW1, SW2 & V_OUT:
Voltage to SGND & PGND
FB, EN ,MODE, SYNC pins:
PGND to SGND
Continuous Power Dissipation
 (Note 3)
Maximum Junction Temperature
(T_J-MAX)
−0.2V to +6.0V
(PGND &
SGND-0.2V) to
(PV_IN + 0.2)
-0.2V to 0.2V
Internally Limited
+125°C
Storage Temperature Range
Maximum Lead Temperature
(Soldering, 10 sec)
−65°C to +150°C
+260°C
Operating Ratings
Input Voltage Range
Recommended Load Current
Junction Temperature (T_J) Range
Ambient Temperature (T_A) Range
 (Note 3)
2.5V to 5.5V
0mA to 1A
−40°C to +125°C
−40°C to +85°C
Thermal Properties
Junction-to-Ambient Thermal Resistance (θ_JA),
Leadless Lead frame Package (Note 5)
34°C/W
Electrical Characteristics (Notes 6, 7) Limits in standard typeface are for T_J = +25°C. Limits in boldface type
apply over the full operating ambient temperature range (−40°C ≤ = T_A ≤ +85°C). Unless otherwise noted, specifications apply to
the LM3668. V_IN = 3.6V = EN, V_OUT = 3.3V. For V_OUT = 4.5/5.0V, V_IN = 4V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V_FB
I_LIM
I_SHDN
I_{Q_PFM}
Feedback Voltage
Switch Peak Current Limit
Shutdown Supply Current
DC Bias Current in PFM
(Note 7)
-3
3
%
Open loop(Note 2)
1.6
1.85
2.05
A
EN =0V
0.01
1
µA
No load, device is not switching
(FB forced higher than
programmed output voltage)
45
60
µA
I_{Q_PWM}
R_DSON(P)
R_DSON(N)
F_OSC
F_SYNC
V_IH
DC Bias Current in PWM
Pin-Pin Resistance for PFET
Pin-Pin Resistance for NFET
Internal Oscillator Frequency
Sync Frequency Range
Logic High Input for EN, MODE/
SYNC pins
PWM Mode, No Switching
Switches P1 and P2
Switches N1 and N2
PWM Mode
V_IN = 3.6V
600
750
µA
130
180
mΩ
100
150
mΩ
1.9
2.2
2.5
MHz
1.6
2.7
MHz
1.1
V
V_IL
Logic Low Input for EN, MODES/
SYNC pins
0.4
V
I_{EN, MODE, SYNC}
EN, MODES/SYNC pins Input
Current
0.3
1
µA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle current limits is activated).
Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%.
Note 3: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP = 125ºC), the maximum power
dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the
following equation: T_A-MAX = T_J-MAX-OP – (θ_JA × P_D-MAX).
Note 4: The Human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 5: Junction-to-ambient thermal resistance (θ_JA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the
JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 101.6mm x 76.2mm x 1.6mm. Thickness of the copper layers are 2oz/1oz/1oz/
2oz. The middle layer of the board is 60mm x 60mm. Ambient temperature in simulation is 22°C, still air.
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special
care must be paid to thermal dissipation issues in board design.
Note 6: All voltage is with respect to SGND.
Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 8: C_IN and C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
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