DS92001 Datasheet, PDF (4/12 Pages) National Semiconductor (TI) – 3.3V B/LVDS-BLVDS Buffer

AC Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3)
Symbol
Parameter
Conditions
Min Typ
LVDS OUTPUT AC SPECIFICATIONS (OUT)
t_LHT
Rise Time (Notes 5, 10)
20% to 80% points
R_L = 50Ω or 27Ω, C_L = 15pF
Figure 3 and Figure 5
0.350 0.6
t_HLT
Fall Time (Notes 5, 10)
80% to 20% points
0.350 0.6
t_PHZ
Disable Time (Active High to Z) R_L = 50Ω, C_L = 15pF
3
t_PLZ
Disable Time (Active Low to Z) Figure 6 and Figure 7
3
t_PZH
Enable Time (Z to Active High)
100
t_PZL
Enable Time (Z to Active Low)
100
t_DJ
LVDS Data Jitter, Deterministic V_ID = 300mV; PRBS = 2²³ − 1 data; V_CM = 1.2V at
(Peak-to-Peak) (Note 9)
400Mbps (NRZ)
t_RJ
LVDS Clock Jitter, Random
V_ID = 300mV; V_CM = 1.2V at 200MHz clock
(Note 9)
f_MAX
Maximum guaranteed
frequency
(Note 11)
V_ID = 200mV, V_CM = 1.2V
200 300
LVCMOS/LVTTL AC SPECIFICATIONS (LOS)
t_PHLLOS
t_PLHLOS
LVTTL Propagation Delay High
to Low (Note 5)
LVTTL Propagation Delay Low
to High (Note 5)
CL = 10pF, IN− = 1V, 1V ≤ IN+ ≤ 1.3V,
Freq. = 10MHz, 50% Duty Cycle
Figures 8, 9
10
15
2
5
t_LHLOS
Rise Time
20% to 80% (Note 5)
1
2
t_HLLOS
Fall Time
80% to 20% (Note 5)
1
1.3
Max Units
1.0
ns
1.0
ns
25
ns
25
ns
120 ns
120 ns
78
ps
36
ps
MHz
20
ns
10
ns
3
ns
3
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V_ID, V_OD, V_TH,
V_TL, and ∆V_OD. V_OD has a value and direction. Positive direction means OUT+ is a more positive voltage than OUT−.
Note 3: All typical are given for V_CC = +3.3V and T_A = +25˚C, unless otherwise stated.
Note 4: Output short circuit current (I_OS) is specified as magnitude only, minus sign indicates direction only.
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and
temperature) range.
Note 6: t_SKD1, |t_PLHD − t_PHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel (a measure of duty cycle).
Note 7: t_SKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same V_CC and within 5˚C of each other within the operating temperature range. This parameter guaranteed by design and characterization.
Note 8: t_SKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. t_SKD4 is defined as |Max − Min| differential propagation delay.
Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test
equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A (digital scope mainframe) with Agilent 86122A
(20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24 picoseconds; t_DJ measured 100 picoseconds, t_RJ measured 60
picoseconds.
Note 10: Propagation delay, rise and fall times are guaranteed by design and characterization to 200MHz. Generator for these tests: 50MHz ≤ f ≤ 200MHz, Zo =
50Ω, tr, tf ≤ 0.5ns. Generator used was HP8130A (300MHz capability).
Note 11: f_MAX test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD ≥ 200mV, Duty Cycle better than 45/55%. This specification
is guaranteed by design and characterization. A minimum is specified, which means that the device will operate to specified conditions from DC to the minimum
guaranteed AC frequency. The typical value is always greater than the minimum guarantee.
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