DS90LT012AH Datasheet, PDF (4/7 Pages) National Semiconductor (TI) – High Temperature 3V LVDS Differential Line Receiver

Parameter Measurement Information (Continued)
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FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
Typical Applications
Balanced System
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FIGURE 3. Point-to-Point Application (DS90LT012AH)
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-003), AN-808,
AN-977, AN-971, AN-916, AN-805, AN-903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 3. This configuration provides a clean signaling
environment for the fast edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically the characteristic
impedance of the media is in the range of 100Ω. The internal
termination resistor converts the driver output (current mode)
into a voltage that is detected by the receiver. Other configu-
rations are possible such as a multi-receiver configuration,
but the effects of a mid-stream connector(s), cable stub(s),
and other impedance discontinuities as well as ground shift-
ing, noise margin limits, and total termination loading must
be taken into account.
The DS90LT012AH differential line receiver is capable of
detecting signals as low as 100 mV, over a ±1V common-
mode range centered around +1.2V. This is related to the
driver offset voltage which is typically +1.2V. The driven
signal is centered around this voltage and may shift ±1V
around this center point. The ±1V shifting may be the result
of a ground potential difference between the driver’s ground
reference and the receiver’s ground reference, the common-
mode effects of coupled noise, or a combination of the two.
The AC parameters of both receiver input pins are optimized
for a recommended operating input voltage range of 0V to
+2.4V (measured from each pin to ground). The device will
operate for receiver input voltages up to V_DD, but exceeding
V_DD will turn on the ESD protection circuitry which will clamp
the bus voltages.
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.001µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB board layers (top to bottom): LVDS
signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
signals may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be < 10mm long). This will help eliminate
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