DS90CF383B Datasheet, PDF (4/11 Pages) National Semiconductor (TI) – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz

Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
TPPos1 Transmitter Output Pulse Position for Bit 1
f = 25
MHz
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
TSTC TxIN Setup to TxCLK IN (Figure 6 )
THTC TxIN Hold to TxCLK IN (Figure 6 )
TCCD
SSCG
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle input
clock is assumed, T_A = −10˚C, and 65MHz for " Min ", T_A = 70˚C,
and 25MHz for " Max ", V_CC = 3.6V
Spread Spectrum Clock support; Modulation frequency with a linear
profile (Note 6)
f = 25
MHz
f = 40
MHz
f = 65
MHz
TPLLS Transmitter Phase Lock Loop Set (Figure 8 )
TPDD Transmitter Power Down Delay (Figure 10 )
Min
−0.45
5.26
10.98
16.69
22.41
28.12
33.84
2.5
0.5
3.011
Typ
0
5.71
11.43
17.14
22.86
28.57
34.29
100KHz ±
2.5%/−5%
100KHz ±
2.5%/−5%
100KHz ±
2.5%/−5%
Max
+0.45
6.16
11.88
17.59
23.31
29.02
34.74
6.062
10
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking
Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
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