DS8907 Datasheet, PDF (4/8 Pages) National Semiconductor (TI) – Phase-Locked Loop Frequency Synthesizer

Timing Diagrams
ENABLE vs CLOCK
CLOCK vs DATA
TL F 7511 – 9
AM FM Frequency Synthesizer (Scan Mode)
TL F 7511 – 10
Timing diagrams are not drawn to scale Scale within any one drawing may not be consistent and intervals are defined positive as drawn
TL F 7511 – 11
SERIAL DATA ENTRY INTO THE DS8907
Serial information entry into the DS8907 is enabled by a low
level on the ENABLE input One binary bit is then accepted
from the DATA input with each positive transition of the
CLOCK input The CLOCK input must be low for the speci-
fied time preceding and following the negative transition of
the ENABLE input
The first two bits accepted following the negative transition
of the ENABLE input are interpreted as address If these
address bits are not 1 1 no further information will be ac-
cepted from the DATA inputs and the internal data latches
will not be changed when ENABLE returns high
If these first two bits are 1 1 then all succeeding bits are
accepted as data and are shifted successively into the in-
ternal shift register as long as ENABLE remains low
Any data bits preceding the 18th to last bit will be shifted
out and thus are irrelevant Data bits are counted as any
bits following two valid address bits (1 1) with the ENABLE
low When the ENABLE input returns high any further serial
data entry is inhibited Upon this positive transition the data
in the internal shift register is transferred into the internal
data latches Note that until this time the states of the inter-
nal data latches have remained unchanged
These data bits are interpreted as follows
Data Bit Position
Data Interpretation
Last
Bit 18 Output (Pin 2)
2nd to Last
Bit 17 Output (Pin 1)
3rd to Last
Bit 16 Output (FM AM) (Pin 20)
4th to Last
Bit 15 Output (Pin 19)
5th to Last
Bit 14 Output (Pin 18)
6th to Last
MSB of dN (2¹²)
7th to Last
(2¹¹)
8th to Last
(2¹⁰)
9th to Last
(2⁹)
10th to Last
(2⁸)
11th to Last
(2⁷)
12th to Last
(2⁶) dN
13th to Last
(2⁵)
14th to Last
(2⁴)
15th to Last
(2³)
16th to Last
17th to Last
18th to Last
-⁽²²⁾
(2¹)
LSB of dN (2⁰)
Note The actual divide code is Na1 i e the number loaded plus 1
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