DS75150 Datasheet, PDF (4/6 Pages) National Semiconductor (TI) – Dual Line Driver

DC Test Circuits (Continued)
I_OS is tested for both input conditions at each of the specified output conditions.
FIGURE 4. I_OS
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FIGURE 5. I_CCH+, I_CCH−, I_CCL+, I_CCL−
AC Test Circuit and Switching Waveforms
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Note 7: The pulse generator has the following characterstics:
duty cycle ≤ 50%, Z_OUT ≅ 50Ω.
Note 8: C_L includes probe and jig capacitance.
FIGURE 6.
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