CD4723BM Datasheet, PDF (4/8 Pages) National Semiconductor (TI) – Dual 4-Bit, 8-Bit Addressable Latch

AC Electrical Characteristics
T_A e 25 C C_L e 50 pF R_L e 200k Input t_r e t_f e 20 ns unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_{PHL tPLH}
t_PLH t_PHL
t_PHL
t_PLH t_PHL
t_THL t_TLH
T_WH T_WL
t_WH t_WL
t_WH
t_SU
t_H
t_SU
t_H
C_PD
Propagation Delay
Data to Output
Propagation Delay
Enable to Output
Propagation Delay
Clear to Output
Propagation Delay
Address to Output
Transition Time
(Any Output)
Minimum Data
Pulse Width
Minimum Address
Pulse Width
Minimum Clear
Pulse Width
Minimum Setup Time
Data to E
Minimum Hold Time
Data to E
Minimum Setup Time
Address to E
Minimum Hold Time
Address to E
Power Dissipation
Capacitance
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
Per Package
(Note 4)
200
400
ns
75
150
ns
50
100
ns
200
400
ns
80
160
ns
60
120
ns
175
350
ns
80
160
ns
65
130
ns
225
450
ns
100
200
ns
75
150
ns
100
200
ns
50
100
ns
40
80
ns
100
200
ns
50
100
ns
40
80
ns
200
400
ns
100
200
ns
65
125
ns
75
150
ns
40
75
ns
25
50
ns
40
80
ns
20
40
ns
15
30
ns
60
120
ns
30
60
ns
25
50
ns
b15
50
ns
0
30
ns
0
20
ns
b50
15
ns
b20
10
ns
b15
5
ns
100
pF
C_IN
Input Capacitance
Any Input
50
75
pF
AC Parameters are guaranteed by DC correlated testing
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device
operation
Note 2 V_SS e 0V unless otherwise specified
Note 3 I_OL and I_OH are tested one output at a time
Note 4 Dynamic power dissipation (P_D) is given by P_D e (C_PD a C_L) V_CC2f a P_Q where C_L e load capacitance f e frequency of operation for further details
see Application Note AN-90 ‘‘54C 74C Family Characteristics’’
4