CD4047BC Datasheet, PDF (4/6 Pages) Fairchild Semiconductor – Low Power Monostable/Astable Multivibrator

Logic Diagram
Special input protection circuit to permit larger input-voltage swings
Truth Table
Function
Terminal Connections
To V_DD
To V_SS
Input Pulse
To
Astable Multivibrator
Free-Running
4 5 6 14 7 8 9 12
True Gating
4 6 14
7 8 9 12
5
Complement Gating
6 14
5 7 8 9 12
4
Monostable Multivibrator
Positive-Edge Trigger
Negative-Edge Trigger
Retriggerable
External Countdown
4 14
4 8 14
4 14
14
5 6 7 9 12
5 7 9 12
5679
5 6 7 8 9 12
8
6
8 12
(See Figure)
Note External resistor between terminals 2 and 3 External capacitor between terminals 1 and 3
Output Pulse
From
10 11 13
10 11 13
10 11 13
10 11
10 11
10 11
(See Figure)
TL F 5969 – 3
Typical Output
Period or
Pulse Width
t_A (10 11) e 4 40 RC
t_A (13) e 2 20 RC
t_M (10 11) e 2 48 RC
(See Figure)
Typical Implementation of External Countdown Option
t_EXT e (N b 1) t_A a (t_M a t_A 2)
TL F 5969 – 4
4