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| CD4034BM Datasheet, PDF (4/12 Pages) National Semiconductor (TI) – 8-Stage TRI-STATE Bidirectional Parallel/Serial Input/Output Bus Register | |||
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AC Electrical Characteristics
TA e 25 C CL e 50 pF RL e 200k input tr e tf e 20 ns unless otherwise specified (Continued)
Symbol
Parameter
Conditions
Min Typ Max Units
tTHL tTLH
Output Transition Time
VDD e 5V
VDD e 10V
VDD e 15V
100 200
ns
50
100
ns
40
80
ns
fCL
Maximum Clock Input Frequency
VDD e 5V
VDD e 10V
VDD e 15V
2
4
5
10
7
14
MHz
MHz
MHz
tWL tWH
Minimum Clock Pulse Width
VDD e 5V
VDD e 10V
VDD e 15V
125 250
ns
50
100
ns
35
70
ns
tRCL tFCL Maximum Clock Rise Fall Time
VDD e 5V
VDD e 10V
VDD e 15V
15
ms
15
ms
15
ms
tSU
Parallel (A or B) and Serial Data
VDD e 5V
Setup Time
VDD e 10V
VDD e 15V
25
70
ns
10
30
ns
7
20
ns
tSU
Control Inputs AE A B P S
VDD e 5V
A S Setup Time
VDD e 10V
VDD e 15V
110 280
ns
35
100
ns
60
60
ns
tWH
Minimum High Level AE A B P S
VDD e 5V
A S Pulse Width
VDD e 10V
VDD e 15V
160 400
ns
70
160
ns
40
90
ns
CIN
Average Input Capacitance
A and B Data I O and A B Control
Input
Any Other Input
7
15
pF
5
75
pF
CPD
Power Dissipation Capacitance
(Note 4)
155
pF
AC Parameters are guaranteed by DC correlated testing
Note 4 CPD determines the no-load power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note
AN-90
Logic Diagram
TL F 5963 â 2
4
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