ADC78H90 Datasheet, PDF (4/16 Pages) National Semiconductor (TI) – 8-Channel, 500 kSPS, 12-Bit A/D Converter

ADC78H90 Converter Electrical Characteristics (Note 8) (Continued)
The following specifications apply for AV_DD = DV_DD = +2.7V to 5.25V, AGND = DGND = 0V, f_SCLK = 8 MHz, f_SAMPLE = 500
KSPS, unless otherwise noted. Boldface limits apply for T_A = T_MIN to T_MAX: all other limits T_A = 25˚C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 7)
Units
ANALOG INPUT CHARACTERISTICS
V_IN
I_DCL
C_INA
Input Range
DC Leakage Current
Input Capacitance
Track Mode
Hold Mode
0 to AV_DD
±1
33
3
V
µA (max)
pF
pF
DIGITAL INPUT CHARACTERISTICS
V_IH
Input High Voltage
V_IL
Input Low Voltage
I_IN
Input Current
C_IND
Digital Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS
DV_DD = +4.75Vto +5.25V
DV_DD = +2.7V to +3.6V
DV_DD = +2.7V to +5.25V
V_IN = 0V or DV_DD
2.4
V (min)
2.1
V (min)
0.8
V (max)
±0.01
±1
µA (max)
2
4
pF (max)
V_OH
Output High Voltage
I_SOURCE = 200 µA, DV_DD = +2.7V to
+5.25V
DV_DD −0.5
V (min)
V_OL
I_OZH,
I_OZL
C_OUT
Output Low Voltage
TRI-STATE^® Leakage Current
TRI-STATE^® Output Capacitance
Output Coding
I_SINK = 200 µA
0.4
V (max)
±1
µA (max)
2
4
pF (max)
Straight (Natural) Binary
POWER SUPPLY CHARACTERISTICS (C_L = 10 pF)
AV_DD,
DV_DD
Analog and Digital Supply Voltages AV_DD ≥ DV_DD
AV_DD = DV_DD = +4.75V to +5.25V,
Total Supply Current, Normal Mode f_SAMPLE = 500 kSPS, f_IN = 40 kHz
I_A + I_D
(Operational, CS low)
Total Supply Current, Shutdown (CS
AV_DD = DV_DD = +2.7V to +3.6V,
f_SAMPLE = 500 kSPS, f_IN = 40 kHz
AV_DD = DV_DD = +4.75V to +5.25V,
f_SAMPLE = 0 kSPS
high)
AV_DD = DV_DD = +2.7V to +3.6V,
f_SAMPLE = 0 kSPS
Power Consumption, Normal Mode \AV_DD = DV_DD = +4.75V to +5.25V
P_D
(Operational, CS low)
AV_DD = DV_DD = +2.7V to +3.6V
Power Consumption, Shutdown (CS AV_DD = DV_DD = +4.75V to +5.25V
high)
AV_DD = DV_DD = +2.7V to +3.6V
AC ELECTRICAL CHARACTERISTICS
1.65
0.5
200
200
8.3
1.5
0.5
0.3
2.7
V (min)
5.25
V (max)
2.3
mA (max)
2.3
mA (max)
nA
nA
12
mW (max)
8.3
mW (max)
µW
µW
f_SCLK
f_SMIN
f_S
t_CONV
DC
Maximum Clock Frequency
Minimum Clock Frequency
Maximum Sample Rate
Conversion Time
SCLK Duty Cycle
8
MHz (min)
50
kHz
500
KSPS (min)
13
SCLK cycles
40
% (min)
50
60
% (max)
t_ACQ
Track/Hold Acquisition Time
Throughput Time
Full-Scale Step Input
Acquisition Time + Conversion Time
3
SCLK cycles
16
SCLK cycles
f_RATE
t_AD
Throughput Rate
Aperture Delay
500
kSPS (min)
4
ns
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