ADC14V155_09 Datasheet, PDF (4/24 Pages) National Semiconductor (TI) – 14-Bit, 155 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs

Pin No.
11
Symbol
CLK+
12
CLK−
DIGITAL I/O
17
18
19
20
21
22
23
24
27
28
29
30
31
32
15
16
D1-/D0-
D1+/D0+
D3-/D2-
D3+/D2+
D5-/D4-
D5+/D4+
D7-/D6-
D7+/D6+
D9-/D8-
D9+/D8+
D11-/D10-
D11+/D10+
D13-/D12-
D13+/D12+
OVR-
OVR+
33
DRDY+
34
DRDY-
ANALOG POWER
1, 6, 9, 37, 40,
41, 48
V_A
2, 5, 10, 38,
39, 42, 47,
Exposed Pad
DIGITAL POWER
AGND
13
V_D
14
DGND
25, 36
V_DR
26, 35
DRGND
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Equivalent Circuit
Description
The clock input pins can be configured to accept either a single-
ended or a differential clock input signal.
When the single-ended clock mode is selected through CLK_SEL/
DF (pin 8), connect the clock input signal to the CLK+ pin and
connect the CLK− pin to AGND.
When the differential clock mode is selected through CLK_SEL/DF
(pin 8), connect the positive and negative clock inputs to the CLK
+ and CLK− pins, respectively.
The analog input is sampled on the falling edge of the clock input.
LVDS digital data output pins that make up the 14-Bit conversion
result. The data is provided in a 2:1 multiplexed manner
synchronous to DRDY+/-.
The even bits should be captured with the rising edge of DRDY and
the odd bits should be captured with the falling edge of DRDY.
D0 is the LSB.
D13 is the MSB.
Over-Range Indicator. This LVDS output is set HIGH when the
input amplitude goes outside the expected 14-Bit conversion range
(0 to 16383).
Data Ready Strobe. This LVDS output is used to clock the output
data. It has the same frequency as the sampling clock. One half of
the data word is output with each edge of this signal - thus
transferring a complete 14-bit word in each cycle of this clock. The
even bits should be captured with the rising edge of DRDY and the
odd bits should be captured with the falling edge of DRDY.
Positive analog supply pins. These pins should be connected to a
quiet +3.3V source and be bypassed to AGND with 0.01 µF and
0.1 µF capacitors located close to the power pins.
The ground return for the analog supply.
Note: Exposed pad on bottom of package must be soldered to
ground plane to ensure rated performance.
Positive digital supply pin. This pin should be connected to a quiet
+3.3V source and be bypassed to DGND with a 0.01 µF and 0.1
µF capacitor located close to the power pin.
The ground return for the digital supply.
Positive driver supply pin for the output drivers. This pin should be
connected to a quiet voltage source of +1.8V and be bypassed to
DRGND with 0.01 µF and 0.1 µF capacitors located close to the
power pins.
The ground return for the digital output driver supply. These pins
should be connected to the system digital ground, but not be
connected in close proximity to the ADC's DGND or AGND pins.
See Section 6.0 (Layout and Grounding) for more details.
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