ADC10D1000 Datasheet, PDF (39/62 Pages) National Semiconductor (TI) – Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS ADC

16.2.2 Extended Control Mode
In Extended Control Mode (ECM), most functions are con-
trolled via the Serial Interface. In addition to this, several of
the control pins remain active. See Table 17 for details. ECM
is selected by setting the ECE Pin to logic-low. If the ECE Pin
is set to logic-high (Non-ECM), then the registers are reset to
their default values. So, a simple way to reset the registers is
by toggling the ECE pin. Four pins on the ADC10D1000 con-
trol the Serial Interface: SCS, SCLK, SDI and SDO. This
section covers the Serial Interface. The Register Definitions
are located at the end of the datasheet so that they are easy
to find, see Section 18.0 Register Definitions.
16.2.2.1 The Serial Interface
The ADC10D1000 offers a Serial Interface that allows access
to the sixteen control registers within the device. The Serial
Interface is a generic 4-wire (optionally 3-wire) synchronous
interface that is compatible with SPI type interfaces that are
used on many micro-controllers and DSP controllers. Each
serial interface access cycle is exactly 24 bits long. A register-
read or register-write can be accomplished in one cycle. The
signals are defined in such a way that the user can opt to
simply join SDI and SDO signals in his system to accomplish
a single, bidirectional SDI/O signal. A summary of the pins for
this interface may be found in Table 15. See Figure 11 for the
timing diagram and Table 13 for timing specification details.
Control register contents are retained when the device is put
into power-down mode.
TABLE 15. Serial Interface Pins
Pin
Name
C4
SCS (Serial Chip Select bar)
C5
SCLK (Serial Clock)
B4
SDI (Serial Data In)
A3
SDO (Serial Data Out)
SCS: Each assertion (logic-low) of this signal starts a new
register access, i.e. the SDI command field must be ready on
the following SCLK rising edge. The user is required to de-
assert this signal after the 24th clock. If the SCS is de-
asserted before the 24th clock, no data read/write will occur.
For a read operation, if the SCS is asserted longer than 24
clocks, the SDO output will hold the D0 bit until SCS is de-
asserted. For a write operation, if the SCS is asserted longer
than 24 clocks, data write will occur normally through the SDI
input upon the 24th clock. Setup and hold times, t_SCS and
t_HCS, with respect to the SCLK must be observed. SCS must
be toggled in between register access cycles.
SCLK: This signal is used to register the input data (SDI) on
the rising edge; and to source the output data (SDO) on the
falling edge. The user may disable the clock and hold it at
logic-low. There is no minimum frequency requirement for
SCLK; see f_SCLK in Table 13 for more details.
SDI: Each register access requires a specific 24-bit pattern at
this input, consisting of a command field and a data field.
When in read mode, the data field is high impedance in case
the bidirectional SDI/O option is used. Setup and hold times,
t_SH and t_SSU, with respect to the SCLK must be observed.
SDO: This output is normally tri-stated and is driven only
when SCS is asserted, the first 8 bits of command data have
been received and it is a READ operation. The data is shifted
out, MSB first, starting with the 8th clock's falling edge. At the
end of the access, when SCS is de-asserted, this output is tri-
stated once again. If an invalid address is accessed, the data
sourced will consist of all zeroes. If it is a read operation, there
will be a bus turnaround time, t_BSU, from when the last bit of
the command field was read in until the first bit of the data field
is written out.
Table 16 shows the Serial Interface bit definitions.
TABLE 16. Command and Data Field Definitions
Bit No.
Name
Comments
1
Read/Write (R/W)
1b indicates a read operation
0b indicates a write operation
2-3
Reserved
Bits must be set to 10b
4-7
A<3:0>
16 registers may be addressed.
The order is MSB first
8
X
This is a "don't care" bit
9-24
D<15:0>
Data written to or read from
addressed register
The serial data protocol is shown for a read and write opera-
tion in Figure 12 and Figure 13, respectively.
FIGURE 12. Serial Data Protocol - Read Operation
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