DP83936AVUL-20 Datasheet, PDF (38/104 Pages) National Semiconductor (TI) – Full Duplex SONICTM-T Systems-Oriented Network Interface Controller with Twisted Pair Interface

6 0 SONIC-T Registers (Continued)
TABLE 6-1 User Registers (Continued)
RA5 – RA0
WATCHDOG COUNTERS
29
2A
SILICON REVISION
28
Access
RW
RW
R
Register
Watchdog Timer
Watchdog Timer 1
Silicon Revision
Symbol
WT0
WT1
SR
Description
(section)
6 4 12
6 4 12
6 4 13
Note 1 These registers can only be read when the SONIC-T is in reset mode (RST bit in the CR is set) The SONIC-T gives invalid data when these registers are
read in non-reset mode
Note 2 This register can only be written to when the SONIC-T is in reset mode This register is normally only loaded by the Load CAM command
Note 3 The Data Configuration registers DCR and DCR2 can only be written to when the SONIC-T is in reset mode (RST bit in CR is set) Writing to these
registers while not in reset mode does not alter the registers
Note 4 The data written to these registers is inverted before being latched That is if a value of FFFFh is written these registers will contain and read back the
value of 0000h Data is not inverted during a read operation
TABLE 6-2 Internal Use Registers (Users should not write to these registers)
(RA5 – RA0)
Access
TRANSMIT REGISTERS
08 (Note 1)
RW
09
RW
0A
RW
0B
RW
0C (Note 2)
RW
20
RW
2F
R
RECEIVE REGISTERS
0F
RW
10
RW
11
RW
12
RW
19
RW
1A
RW
1B
RW
1C
RW
1F
RW
ADDRESS GENERATORS
1D
RW
1E
RW
Register
Transmit Packet Size
Transmit Fragment Count
Transmit Start Address 0
Transmit Start Address 1
Transmit Fragment Size
Temporary Transmit Descriptor Address
Maximum Deferral Timer
Current Receive Buffer Address 0
Current Receive Buffer Address 1
Remaining Buffer Word Count 0
Remaining Buffer Word Count 1
Temporary Receive Buffer Address 0
Temporary Receive Buffer Address 1
Temporary Buffer Word Count 0
Temporary Buffer Word Count 1
Last Link Field Address
Address Generator 0
Address Generator 1
Symbol
TPS
TFC
TSA0
TSA1
TFS
TTDA
MDT
CRBA0
CRBA1
RBWC0
RBWC1
TRBA0
TRBA1
TBWC0
TBWC1
LLFA
ADDR0
ADDR1
Description
(section)
55
55
55
55
55
554
644
542 5442
542 5442
542 5442
542 5442
5462
5462
5462
5462
none
none
none
Note 1 The data that is read from these registers is the inversion of what has been written to them
Note 2 The value that is written to this register is shifted once in 16-bit mode and shifted twice in 32-bit mode
TABLE 6-3 National Factory Test Registers (Users should not access these registers)
(RA5 – RA0)
30

3E
Access
RW
Register
These registers are for factory use only Users must not
address these registers or improper SONIC-T operation
can occur
Symbol
none
Description
(section)
none
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