ADC12EU050_0811 Datasheet, PDF (35/48 Pages) National Semiconductor (TI) – Ultra-Low Power, Octal, 12-bit, 40-50 MSPS Sigma-Delta Analog-to-Digital Converter

Top Control Register
Address:
Attributes
00h
Write Only.
Register 01h reads back contents of register 00h, if CBR is set.
The Top Control Register is the basic initialization and control register for the device.
Description
Default
b[7]
b[6]
Reserved
0
0
b[5]
CBR
0
b[4]
b[3]
b[2]
b[1]
b[0]
40/50 SRES SPIOD SLEEP
PD
0
0
0
0
0
HEX
00 h
Bit
Description
7:6
Reserved. Write as zero for future compatibility.
5
CBR: Control Bus Read. When asserted register 00h (this register) can be read, but no other registers.
When de-asserted all other registers can be read, but not register 00h.
0
Register 00h cannot be read from address 01h. All other registers can be read back.
1
Register 00h can be read from address 01h. All other registers cannot be read back.
4
40/50: Selects the ADC sample rate. This bit should be set according to the applied input clock to obtain
optimal performance.
0
45-50MSPS
1
40-45MSPS
3
SRES: Software Reset. When asserted the software reset will reset the whole device. SRES performs
the same function as the hardware reset (RST pin).
The SRES is self clearing in approximately 2µs.
0
Software Reset Inactive
1
Software Reset Active
2
SPIOD: SPI Open Drain mode.
0
Digital Logic Output
1
Open Drain Mode. Enables SPI Driver to operate above V_DR
1
SLEEP: Sleep Mode. Powers down the device with the exception of the PLL and the reference blocks.
The time to wake-up from sleep mode is < 10µs.
0
Sleep Mode Inactive
1
Sleep Mode Active
0
PD: Power Down Mode. Completely powers down the device. The power up time is approximately
20ms.
0
PD Mode Inactive, device operates normally
1
PD Mode Active, device powered down
35
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