CS9211 Datasheet, PDF (32/62 Pages) National Semiconductor (TI) – Geode CS9211 Graphics Companion Flat Panel Display Controller

Functional Description (Continued)
Table 3-13. Dithering Programming Bits
Bit
Name
Description
Offset 40Ch-40Fh
12
DITHER_RAM_
ROM_SEL
6:4
NO_OF_FRM
INTENSITIES
3:1
DITH_BITS
0
DITH_ENB
Offset 424h-427h
7
DITHER_
RAM_ACCESS
6
DITHER_
RAM_UPDT
5:0
DITHER_
RAM_ADDR
Offset 428h-42Bh
31:0
RAM_DATA
Dither and Frame Rate Control Register (R/W)
Reset Value = 00000000h
Dither RAM or ROM Select: This bit selects either internal ROM or internal RAM as the source of the
dither patterns.
0 = Selects fixed (internal to CS9211) ROM for dither patterns (Default).
1 = Selects programmable (internal to CS9211) RAM for dither patterns.
To update the dither RAM, this bit must = 1.
Note: See Offset 424h[6].
Number Of FRM Intensities: The value set by bits [6:4] is the number of intensities that will exist due to
Frame Rate Modulation, prior to dithering. This field selects how many of the incoming most significant
(MS) data bits (per color) are used to generate the FRM intensities .
000 = Two FRM intensities (selects 1 MS (most significant) bit for use by FRM).
001 = Four FRM intensities (selects 2 MS bits for use by FRM).
010 = Eight FRM intensities (selects 3 MS bits for use by FRM).
011 = Sixteen FRM intensities (selects 4 MS bits for use by FRM).
100 = Thirty two FRM intensities (selects 5 MS bits for use by FRM).
101, 110, 111 = Reserved.
Dithering Bits Select: This field is used to select the number of bits to be used for the dithering pattern.
Dither bits are the least-significant bits of each pixel’s color value.
000 = Reserved
001 = Selects 5 bits as dither bits. Number of FRM intensities should be 2 (i.e., bits [6:4] = 000).
010 = Selects 4 bits as dither bits. Number of FRM intensities should be 4 (i.e., bits [6:4] = 001).
011 = Selects 3 bits as dither bits. Number of FRM intensities should be 8 (i.e., bits [6:4] = 010).
100 = Selects 2 bits as dither bits. Number of FRM intensities should be 16 (i.e., bits [6:4] = 011).
101 = Selects 1 bit as a dither bit. Number of FRM intensities should be 32 (i.e., bits [6:4] = 100).
Dithering Enable: Enable/disable dithering. The dither bit must be enabled in order for dither RAM
reads or writes to occur. When this bit is cleared, the internal dither RAM is powered down.
0 = Dither disable - The dithering function is turned off. When the dither is disabled, dither bits [3:1] do
not have any effect and the dither RAM is not accessible.
1 = Dither enable. The dither functions with the number of dither bits as set in [3:1]
Dither RAM Control and Address Register
Reset Value = 00000000h
Dither RAM Access Bit: Allows reads and writes to and from dither RAM.
0 = Disable (Do not allow reads or writes).
1 = Enable (Allow reads and writes).
To perform dither RAM reads and writes, bits 7 and 6 must be set to 1. In addition, Offset 40Ch bits 12
and 0 must be set to 1. If any of these bits are not set to 1, the RAM goes into power-down mode.
Dither RAM Update: This bit works in conjunction with bit 7. If this bit is enabled, it allows the data to
update the RAM.
0 = Disable (do not allow dither RAM access).
1 = Enable (allow dither RAM access).
To perform dither RAM reads and writes, bits 7 and 6 must be set to 1. In addition, Offset 40Ch bits 12
and 0 must be set to 1. If any of these bits are not set to 1, the RAM goes into power-down mode.
Dither RAM Address: This 6-bit field specifies the address to be used for the next access to the dither
RAM. Each access to the data register automatically increments the RAM address register. If non-
sequential access is made to the dither RAM, the address register must be reloaded before each non-
sequential data block.
RAM Data Register (R/W)
Reset Value = 00000000h
RAM Data: This 32-bit field contains the read or write data for the RAM access.
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