ADC08D500_08 Datasheet, PDF (32/38 Pages) National Semiconductor (TI) – High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D500 will function with the CAL pin held high
at power up, but no calibration will be done and performance
will be impaired. A manual calibration, however, may be per-
formed after powering up with the CAL pin high. See On-
Command Calibration Section 2.4.2.2.
The internal power-on calibration circuitry comes up in an un-
known logic state. If the clock is not running at power up and
the power on calibration circuitry is active, it will hold the ana-
log circuitry in power down and the power consumption will
typically be less than 200 mW. The power consumption will
be normal after the clock starts.
2.4.2.2 On-Command Calibration
An on-command calibration may be run at any time in NOR-
MAL (non-DES) mode only. Do not run a calibration while
operating the ADC in Auto DES Mode.
If the ADC is operating in Auto DES mode and a calibration
cycle is required then the controlling application should bring
the ADC into normal (non DES) mode before an On Com-
mand calibration is initiated. Once calibration has completed,
the ADC can be put back into Auto DES mode.
To initiate an on-command calibration, bring the CAL pin high
for a minimum of 80 input clock cycles after it has been low
for a minimum of 80 input clock cycles. Holding the CAL pin
high upon power up will prevent execution of power-on cali-
bration until the CAL pin is low for a minimum of 80 input clock
cycles, then brought high for a minimum of another 80 input
clock cycles. The calibration cycle will begin 80 input clock
cycles after the CAL pin is thus brought high. The CalRun
signal should be monitored to determine when the calibration
cycle has completed. When an on-command calibration is
executed, the CAL pin must be held low for 80 input clock
cycles and then low for 80 input clock cycles before the Cal-
Run pin is activated to indicate that a calibration is taking
place. When the CalRun pin is activated, all outputs including
the DCLK outputs are deactivated and enter a high
impedance state. After the calibration cycle is finished and the
CalRun pin is low, the outputs, including DCLK, are active
again but require a short settling period, typically around
100ns. Because the DCLK outputs are not activated during a
calibration cycle, they are not recommended for use as a sys-
tem clock.
The minimum 80 input clock cycle sequences are required to
ensure that random noise does not cause a calibration to be-
gin when it is not desired. As mentioned in section 1.1.1 for
best performance, a self calibration should be performed 20
seconds or more after power up and repeated when the op-
erating temperature changes significantly according to the
particular system performance requirements. ENOB drops
slightly as junction temperature increases and executing a
new self calibration cycle will essentially eliminate the
change.
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in Section 1.1.1. The calibration delay values
allow the power supply to come up and stabilize before cali-
bration takes place. With no delay or insufficient delay, cali-
bration would begin before the power supply is stabilized at
its operating value and result in non-optimal calibration coef-
ficients. If the PD pin is high upon power-up, the calibration
delay counter will be disabled until the PD pin is brought low.
Therefore, holding the PD pin high during power up will further
delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling
time of the power supply.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these clock signals. That is, the
output data transition can be set to occur with either the rising
edge or the falling edge of the DCLK signal, so that either
edge of that clock signal can be used to latch the output data
into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchronized
with (changes with) the rising edge of the DCLK+ (pin 82).
When OutEdge is low, the output data is synchronized with
the falling edge of DCLK+.
At the very high speeds of which the ADC08D500 is capable,
slight differences in the lengths of the clock and data lines can
mean the difference between successful and erroneous data
capture. The OutEdge pin is used to capture data on the
DCLK edge that best suits the application circuit and layout.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
For short LVDS lines and low noise systems, satisfactory per-
formance may be realized with the FSR input low. If the LVDS
lines are long and/or the system in which the ADC08D500 is
used is noisy, it may be necessary to tie the FSR pin high.
2.4.5 Dual Edge Sampling
The Dual Edge Sampling (DES) feature causes one of the two
input pairs to be routed to both ADCs. The other input pair is
deactivated. One of the ADCs samples the input signal on one
clock edge, the other samples the input signal on the other
clock edge. The result is a 1:4 demultiplexed output with a
sample rate that is twice the input clock frequency.
To use this feature in the non-enhanced control mode, allow
pin 127 to float and the signal at the "I" channel input will be
sampled by both converters. The Calibration Delay will then
only be a short delay.
In the enhanced control mode, either input may be used for
dual edge sampling. See Section 1.1.5.1.
IMPORTANT NOTES:
1) For the Extended Control Mode - When using the Auto-
matic Clock Phase Control feature in dual edge sampling
mode, it is important that the automatic phase control is dis-
abled (set bit 14 of DES Enable register Dh to 0) before the
ADC is powered up. Not doing so may cause the device not
to wake up from the power down state.
2) For the Non-Extended Control Mode - When the AD-
C08D1000 is powered up and DES mode is required, ensure
that pin 127 (CalDly/DES/SCS) is initially pulled low during or
after the power up sequence. The pin can then be allowed to
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