PC8374T Datasheet, PDF (31/48 Pages) National Semiconductor (TI) – SafeKeeper Desktop Trustedl/O

2.0 Device Characteristics (Continued)
2.4.3 Clock Timing
High-Frequency Clock Timing
Symbol Figure Clock Input Parameters
Reference
Conditions
CLOCKI14
Min
Typ
Max
Units
t_CH
8 _{Clock High Pulse Width}¹
20
ns
t_CL
8 _{Clock Low Pulse Width}¹
20
ns
t_CP
8 _{Clock Period}¹ _(50%-50%)
69.14
69.84
70.54
ns
F_CK
− Clock Frequency
F_CKTYP − 1% 14.31818 F_CKTYP + 1% MHz
t_CR
8 _{Clock Rise Time}¹ _{(VIL to VIH)}
5²
ns
t_CF
8 _{Clock Fall Time}¹ _{(VIH to VIL)}
5²
ns
RE PCI_RESET
t_CE
9 Clock Generator Enable
to Clock Generator
enabled
80
µs
1. Not tested. Guaranteed by design.
2. Recommended value.
Sym. Fig. Internal Clock Parameter
Reference
Conditions
t_CP
F_CK
t_48MD
8 _{Clock Period}¹ _(50%-50%)
− Clock Frequency
9 _{Clock Wake-Up Time}¹
After Clock
Generator enabled
1. Not tested. Guaranteed by characterization.
INT48M
Min
Typ
Max
20.83
48
500
Units
ns
MHz
µs
t_CH
t_CP
V_IH
V_IH
V_IH
V_IL
V_IL
V_IL
t_CL
t_CF
t_CR
Figure 8. High-Frequency Clock Waveform Timing
V_DD3 (Power) ^VDD3ONmin
t_CP (CLOCKI14)
CLOCKI14
(14.31818 MHz)
t_CE
PCI_RESET
Enable Clock Generator
(Internal)
48 MHz Clock
CKVALID bit
(Internal)
(Internal)
t_48MD
t_CP (48 MHz)
Figure 9. CLOCKI14 and Internal 48 MHz Clock Timing
Revision 1.1
31
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