LMX2487E Datasheet, PDF (31/38 Pages) Texas Instruments – Low-Power Dual PLLatinum Frequency Synthesizers

2.5 R4 REGISTER
This register controls the conditions for the RF PLL in Fastlock.
REGISTER
R4
23 22 21 20 19 18 17 16 15 14 13 12
11 10 9
8 7654 3 2 1 0
DATA[19:0]
C3 C2 C1 C0
ATPU 0
1
0
0
0
DITH
[1:0]
FM
[1:0]
0
OSC_
2X
OSC_
OUT
IF_
CPP
RF_
CPP
IF_P
MUX
[3:0]
1001
2.5.1 MUX[3:0] Frequency Out & Lock Detect MUX
These bits determine the output state of the Ftest/LD pin.
MUX[3:0]
Output Type
Output Description
0
0
0
0
High Impedance
Disabled
0
0
0
1
Push-Pull
General purpose output, Logical “High”
State
0
0
1
0
Push-Pull
General purpose output, Logical “Low”
State
0
0
1
1
Push-Pull
RF & IF Digital Lock Detect
0
1
0
0
Push-Pull
RF Digital Lock Detect
0
1
0
1
Push-Pull
IF Digital Lock Detect
0
1
1
0
Open Drain
RF & IF Analog Lock Detect
0
1
1
1
Open Drain
RF Analog Lock Detect
1
0
0
0
Open Drain
IF Analog Lock Detect
1
0
0
1
Push-Pull
RF & IF Analog Lock Detect
1
0
1
0
Push-Pull
RF Analog Lock Detect
1
0
1
1
Push-Pull
IF Analog Lock Detect
1
1
0
0
Push-Pull
IF R Divider divided by 2
1
1
0
1
Push-Pull
IF N Divider divided by 2
1
1
1
0
Push-Pull
RF R Divider divided by 2
1
1
1
1
Push-Pull
RF N Divider divided by 2
2.5.2 IF_P -- IF Prescaler
When this bit is set to 0, the 8/9 prescaler is used. Otherwise the 16/17 prescaler is used.
IF_P
0
1
IF Prescaler
8/9
16/17
Maximum Frequency
800 MHz
800 MHz
2.5.3 RF_CPP -- RF PLL Charge Pump Polarity
RF_CPP
0
1
RF Charge Pump Polarity
Negative
Positive (Default)
2.5.4 IF_CPP -- IF PLL Charge Pump Polarity
For a positive phase detector polarity, which is normally the case, set this bit to 1. Otherwise set this bit for a negative phase
detector polarity.
IF_CPP
0
1
IF Charge Pump Polarity
Negative
Positive
31
www.national.com