THS4531A Datasheet, PDF (30/51 Pages) Texas Instruments – Ultra Low Power, Rail-to-Rail Output, Fully-Differential Amplifier

THS4531A
SLOS823A – DECEMBER 2012 – REVISED JANUARY 2013
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Power Down
The power down pin is internally connected to a CMOS stage which must be driven to a minimum of 2.1V to
ensure proper high logic.
VS+
Internal
PD Circuit
PD
VS±
Figure 77. Simplified Power Down Internal Circuit
If 1.8V logic is used to drive the pin, a shoot through current of up to 100µA may develop in the digital logic
causing the overall quiescent current to exceed the 2uA of maximum disabled quiescent current specified in the
electrical characteristics.
In order to properly interface to 1.8V logic with minimal increase in additional current draw, a logic-level translator
like the SN74AVC1T45 can be used.
Alternatively, the same function may be achieved using a diode and pull up resistor shown below.
3V
1.8V
Controller
VS+
RPU
THS4531A
D
PD
Figure 78. THS4531A Power Down Interface to 1.8V Logic Microcontroller
The voltage seen at the power down pin will be a function of the supply voltage, input logic level, and diode drop.
As long as the diode is forward biased, the power down voltage will be determined by:
V_PD = V_L + V_f
(3)
Where VL is the logic level voltage and Vf is the forward voltage drop across the diode.
This means for 1.8V logic, the forward voltage of the diode should be greater than 0.3V but less than 0.7V in
order to keep the power down logic level above 2.1V and less than 0.7V respectively.
For example, if we select 1N914 as the diode with a forward voltage of approximately 0.4V, the translated logic
voltages will be 0.4V for disabled operation and 2.2V for enabled operation.
The additional current draw can be determined by:
i_PD
V_CC
=
- (V_L
R_PU
+ V_f
)
(4)
This equation shows that larger values of RPU result in a smaller additional current. A reasonable value of RPU
may be 500kΩ where we can expect to see an additional current draw of 5.2µA while the device is in operation
and 1.6µA when disabled.
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