ADC08B3000_08 Datasheet, PDF (30/44 Pages) National Semiconductor (TI) – 8-bIT, 3gsps, High Performance, Low Power A/D Converter with 4K Buffer

TABLE 1. Features and Modes
Feature
SDR or DDR Clocking
DDR Clock Phase
SDR Data transitions with rising or
falling DRDY edge
Power-On Calibration Delay
Full-Scale Range
Input Offset Adjust
Sample Clock Phase Adjustment
Test Pattern Output
Normal Control Mode
Selected with pin 4
Not Selectable (0° Phase Only)
Selected with pin 4
Delay Selected with pin 127
Two ranges selected with pin 14 as
described in the Electrical Table.
Not possible
Not possible
Not possible
Extended Control Mode
Selected with nDE in the Configuration
Register (address 1h; bit 10). When the
device is in DDR mode, address 1h, bit 8
must be set to 0b.
Selected with DCP in the Configuration
Register (address 1h; bit 11).
Selected with OE in the Configuration
Register (address 1h; bit 8).
Short delay only.
512 step adjustments possible over a
nominal range of 560 mV to 840 mV by
using the Full-Scale Voltage Register
(address 3h; bits 7 thru 15).
Up to ±45 mV adjustment in 512 steps in the
Offset Adjust Register (address 2h; bits 7
thru 15).
The clock phase can be adjusted manually
through the Fine & Coarse registers
(address Dh and Eh).
A test pattern can be made present at the
data outputs by selecting TPO in the Test
Pattern Register (address Fh; bit 11).
The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 2.
TABLE 2. Extended Control Mode Operation
(Pin 14 Floating)
Feature
Extended Control Mode
Default State
Calibration Delay
Short Delay
Full-Scale Range
700 mV nominal
Input Offset Adjust
0 mV
Clock Phase Adjust - Fine
0 ps Phase Adjust
Clock Phase Adj - Course
0 ps Phase Adjust
Duty Cycle Stabilizer
Enabled
DDR Clock Phase
90° phase aligned
DDR Enable
Single Data Rate, SDR
Capture Buffer Size
4K bytes
Auto-Stop Write
Writes to Capture Buffer will
stop automatically
Two Port Enable
Data on data D1 only
Output Edge
Falling edge of DRDY
Test Pattern Output
No test pattern
Differential ADCCLK_RST
Enable
Single-ended
ADCCLK_RST
1.3 THE SERIAL INTERFACE
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS). Eight write only registers are acces-
sible through this serial interface. Registers are write only and
can not be read back.
SCS: This signal must be asserted low to access a register
through the serial interface. Setup and hold times with respect
to the SCLK must be observed.
SCLK: Serial data input is accepted at the rising edge of this
signal. There is no minimum frequency requirement of this
signal.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram of Figure 2.
Each Register access consists of 32 bits, as shown in of the
Timing Diagrams. The fixed header pattern is 0000 0000 0001
(eleven zeros followed by a 1). The loading sequence is such
that a "0" is loaded first. The next 4 bits are the address of the
register that is to be written to and the last 16 bits are the data
written to the addressed register. The addresses of the vari-
ous registers are indicated in Table 3. Refer to the Register
Description (Section 1.4 REGISTER DESCRIPTION) for in-
formation on the data to be written to the registers.
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
IMPORTANT NOTE: The Serial Interface should not be ac-
cessed while the ADC is undergoing a calibration cycle. Doing
so will impair the performance of the device until it is re-cali-
brated correctly. Programming the serial registers will also
reduce dynamic performance of the ADC for the duration of
the register access time.
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