TP3094 Datasheet, PDF (3/19 Pages) National Semiconductor (TI) – Quad PCM Codec/Filter

Pin Descriptions
MCLK (input)
Master and PCM bit clock input. Must be either
1.536MHz/1.544MHz, 2.048MHz, 4.096MHz or
8.192MHz. Its value is automatically detected in-
ternally on power up with the valid frame sync in-
put.
AVCC0, AVCC1
Positive supply pins for the analog circuitry.
AVCC0 is for channel 0 and channel 1. AVCC1
is for channel 2 and channel 3.
AVCC0=AVCC1=+5V ±5%. These two pins
should be connected together outside the device.
AGND0, AGND1
Analog ground. All analog signals are referenced
to AGND0 and AGND1. AGND0 is the analog
ground for channel 0 and channel 1. AGND1 is
the analog ground for channel 2 and channel 3.
These two pins should be connected together
outside the device.
DVCC
Positive supply for the digital circuitry.
DVCC=+5V ±5%.
DGND
Digital ground. All logic signals are referenced to
DGND. This ground has to be connected to the
ground of other digital devices at board level.
Analog ports
VXI0-, VXI1-, VXI2-, VXI3- (inputs)
Inverting analog inputs of the transmit input am-
plifiers of channels 0-3. They are referenced to an
internal reference voltage of about 2.4V.
GXO0, GXO1, GXO2, GXO3 (outputs)
Outputs of the transmit input amplifiers of chan-
nels 0-3. They are referenced to an internal refer-
ence voltage of about 2.4V
VRO0, VRO1, VRO2, VRO3 (ouputs)
Analog outputs of the receive amplifiers for chan-
nels 0-3. They are referenced to an internal refer-
ence voltage of about 2.4V
PCM Port
DX (ouput)
Transmit PCM data output. Serial PCM data is
shifted out on the rising edge of MCLK during the
assigned transmit time-slot. Tristated when the
assigned transmit time-slot is not active.
TSx (ouput)
Open drain output that pulses low during the as-
signed transmit time-slots (for all four channels).
DR (input)
Receive PCM data input. Serial PCM data is
shifted into the device on the falling edge of
MCLK during the assigned receive time-slot.
FSX0, FSR0 (inputs)
Transmit and Receive Frame synchronization in-
puts for channel 0. They identify the beginning of
a new frame in the transmit and receive direction.
They are 8 KHz logic signals, and must be syn-
chronous to MCLK. Short Frame Sync and Long
Frame Sync are both supported.
In 32-bit mode these signals constitute the 8kHz
reference for all channels. Only Short Frame
Sync is supported in 32-bit mode.
FSX1, FSR1 (inputs/outputs)
Transmit and Receive Frame synchronization in-
puts for channel 1.
In 32-bit mode these pins become outputs and
generate a frame sync signal with the last bit of
the 32-bit stream, in order to allow to cascade an-
other TP3094 in 32-bit mode. FSX1 is the Trans-
mit Frame output and FSR1 is the Receive Frame
output.
FSX2,FSX3, FSR2,FSR3 (inputs)
Transmit and Receive Frame synchronization in-
puts for channel 2 and 3. These pins are recom-
mended to be connected to analog ground when
in 32-bit mode.
A/u LAW select (input)
A/u law select. Through this pin either A-law
(+5V) or u-law (0V) is selected.
PDN0-3 (input)
Power Down control signals. Each channel has a
dedicated Power Down input. When active high,
these pins set the low power mode, shutting down
most of the circuitry dedicated to it and reducing
the power consumption. The relative analog out-
puts VROi and GXOi, and the digital output DX
are put in high impedance.
TST (input)
Test Modes Enable. When active (HIGH), togeth-
er with the PDNi pins selects one of the available
test modes (see the text for a full description of
these modes).
PCMMode (input)
PCM Mode selection. When this signal is LOW
(0V), the 8 bit mode is selected and each channel
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