TP3076 Datasheet, PDF (3/18 Pages) National Semiconductor (TI) – COMBO II Programmable PCM CODEC/Filter for ISDN and Digital Phone Applications

Functional Description (Continued)
The desired modes for all programmable functions may be
initialized via the control port prior to a Power-up command.
POWER-DOWN STATE
Following a period of activity in the powered-up state the
power-down state may be re-entered by writing any of the
control instructions into the serial control port with the “P” bit
set to “1” as indicated in Table 1. It is recommended that the
chip be powered down before writing any additional instruc-
tions. In the power-down state, all non-essential circuitry is
de-activated and the D_X1 output is in the high impedance
TRI-STATE condition.
The data stored in the Gain Control registers, the LDR and
ILR, and all control bits remain unchanged in the
power-down state unless changed by writing new data via
the serial control port, which remains active. The outputs of
the Interface Latches also remain active, maintaining the
ability to monitor and control the SLIC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VF_XI, is a high impedance input.
No external components are necessary to set the gain. Fol-
lowing this is a programmable gain/attenuation amplifier
which is controlled by the contents of the Transmit Gain Reg-
ister (see Programmable Functions section). An active
pre-filter then precedes the 3rd order high-pass and 5th or-
der low-pass switched capacitor filters. The A/D converter
has a compressing characteristic according to the standard
CCITT A or µ255 coding laws, which must be selected by a
control instruction during initialization (see Table 1 and Table
2). A precision on-chip voltage reference ensures accurate
and highly stable transmission levels. Any offset voltage aris-
ing in the gain-set amplifier, the filters or the comparator is
canceled by an internal auto-zero circuit.
Each encode cycle begins immediately following the as-
signed Transmit time-slot. The total signal delay referenced
to the start of the time-slot is approximately 165 µs (due to
the Transmit Filter) plus 125 µs (due to encoding delay),
which totals 290 µs. Data is shifted out on D_X1 during the se-
lected time slot on eight rising edges of BCLK.
DECODER AND RECEIVER FILTER
PCM data is shifted into the Decoder’s Receive PCM Regis-
ter via the D_R1 pin during the selected time-slot on the 8 fall-
ing edges of BCLK. The Decoder consists of an expanding
DAC with either A or µ255 law decoding characteristic, which
is selected by the same control instruction used to select the
Encode law during initialization. Following the Decoder is a
5th order low-pass switched capacitor filter with integral Sin
x/x correction for the 8 kHz sample and hold. A program-
mable gain amplifier, which must be set by writing to the Re-
ceive Gain Register, is included, and finally a Power Ampli-
fier capable of driving a 300Ω load to ±3.5V, a 600Ω load to
±3.8V or a 15 kΩ load to ±4.0V at peak overload.
TABLE 1. Programmable Register Instructions
Function
Byte 1 (Notes 1, 2, 3)
Byte 2 (Note 1)
7654321076543210
Single Byte Power-Up/Down
PXXXXX0X
None
Write Control Register
P000001X
See Table 2
Read-Back Control Register
P000011X
See Table 2
Write to Interface Latch Register
P000101X
See Table 4
Read Interface Latch Register
P000111X
See Table 4
Write Latch Direction Register
P001001X
See Table 3
Read Latch Direction Register
P001011X
See Table 3
Write Receive Gain Register
P010001X
See Table 8
Read Receive Gain Register
P010011X
See Table 8
Write Transmit Gain Register
P010101X
See Table 7
Read Transmit Gain Register
P010111X
See Table 7
Write Receive Time-Slot/Port
P100101X
See Table 6
Read-Back Receive Time-Slot/Port
P100111X
See Table 6
Write Transmit Time-Slot/Port
P101001X
See Table 6
Read-Back Transmit Time-Slot/Port
P101011X
See Table 6
Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI or CO pin. X = don’t care.
Note 2: “P” is the power-up/down control bit, see Power-up/Down Control section. (“0” = Power Up, “1” = Power Down)
Note 3: Other register address codes are invalid and should not be used.
A decode cycle begins immediately after the assigned re-
ceive timeslot, and 10 µs later the Decoder DAC output is
updated. The total signal delay is 10 µs plus 120 µs (filter de-
lay) plus 62.5 µs (¹â„2 frame) which gives approximately 190
µs.
PCM INTERFACE
The FS_X and FS_R frame sync inputs determine the begin-
ning of the 8-bit transmit and receive time-slots respectively.
They may have any duration from a single cycle of BCLK
HIGH to one MCLK period LOW. Two different relationships
may be established between the frame sync inputs and the
actual time-slots on the PCM busses by setting bit 3 in the
Control Register (see Table 2). Non-delayed data mode is
similar to long-frame timing on the TP3050/60 series of de-
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