SCAN15MB200 Datasheet, PDF(3/12 Page) National Semiconductor (TI) – Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6

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SCAN15MB200 Datasheet, PDF (3/12 Pages) National Semiconductor (TI) – Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6

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Pin Descriptions (Continued)

Name

VDD

GND

LLP Pin

Number

6, 12, 37,

43, 48

(Note 2)

I/O, Type

I, Power VDD = 3.3V Â±0.3V.

Description

I, Power

Ground reference for LVDS and CMOS circuitry.

For the LLP package, the DAP is used as the primary GND connection to the device. The

DAP is the exposed metal contact at the bottom of the LLP-48 package. It should be

connected to the ground plane with at least 4 vias for optimal AC and thermal performance.

Note 1: For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).

Note 2: Note that the DAP on the backside of the LLP package is the primary GND connection for the device when using the LLP package.

Note 3: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the SCAN15MB200 device have been optimized

for point-to-point backplane and cable applications.

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