LP265 Datasheet, PDF (3/10 Pages) National Semiconductor (TI) – Micropower Programmable Quad Comparator

Electrical Characteristics (Continued) (Note 8) High power V_Seg15V I_SETe100 mA
Symbol
Parameter
Conditions
LP365A
LP365
Tested
Typ
Limit
Design
Tested
Limit
Typ
Limit
Design
Limit
Units
(Limit)
(Note 5) (Note 6)
(Note 5) (Note 6)
V_OS
Input Offset
Voltage
I_OS
Input Offset
Current
V_CMe0V
R_Se100
V_CMe0V
LP265
1
3
6
3
6
mV
9
(Max)
5
50
100
10
90
200
nA
10
90
500
(Max)
I_B
Input Bias
V_CMe0V
60
200
500
80
300
500
nA
Current
LP265
80
300
800
(Max)
A_VOL
Large Signal
Voltage Gain
R_Le15k
500
100
100
500
100
100
V mV
(Min)
V_CM
Input Common-
Mode Voltage
Range
b15
13
b15
13
b15
13
b15
13
V
(Max)
V
(Min)
CMRR
Common-Mode b15V^sV_CM
85
75
Rejection Ratio ^s13V
70
80
75
dB
70
(Min)
PSRR
Supply Voltage
Rejection Ratio
g10VsV_S
s g _15V
80
70
70
75
70
dB
70
(Min)
I_S
Supply Current
All Inputse0V
26
3
33
28
35
37
mA
R_Le % LP265
28
35
43
(Max)
V_OH
Output Voltage V_Ce5V
High
V_Ee0V
R_Le100k
V_OL
Output Voltage V_Ee0V
Low
49
45
04
04
V
49
45
(Min)
V
04
04
(Max)
I_SINK
Output Sink
Current
V_Ee0V
V_Oe0 4V
10
8
55
75
6
4
mA
(Min)
I_LEAK
Output Leakage
Current
V_Ce15V
V_E e b15V
5
50
5000
5
50
5000
nA
(Max)
t_R
Response Time V_CCe5V
V_Ee0V
R_Le5k
10
10
ms
C_Le10 pF
(Note 7)
Note 1 The input voltage is not allowed to go 0 3V above V^a or b0 3V below V^b as this will turn on a parasitic transistor causing large currents to flow through
the device
Note 2 Short circuits from the output to V^a may cause excessive heating and eventual destruction The current in the output leads and the V_E lead should not be
allowed to exceed 30 mA The output should not be shorted to V^b if V_Es(V^b) a 7V
Note 3 For operating at elevated temperatures these devices must be derated based on a thermal resistance of i_jA and T_j max T_jeT_Aai_jAP_D
Note 4 Boldface numbers apply at temperature extremes All other numbers apply at T_AeT_je25 C V^a e5V V^be0V I_SETe10 mA R_Le100k and
V_Ce5V as shown in the Typical Connection diagram
Note 5 Guaranteed and 100% production tested
Note 6 Guaranteed (but not 100% production tested) over the operating temperature and supply voltage ranges These limits are not used to calculate out-going
quality levels
Note 7 The response time specified is for a 100 mV input step with 5 mV overdrive
Note 8 Boldface numbers apply at temperature extremes All other numbers apply at T_AeT_je25 C V^a e a 15V V^beb15V I_SETe100 mA R_Le100k and
V_Ce5V as shown in the Typical Connection diagram
Note 9 See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices
Note 10 Human body model 1 5 kX in series with 100 pF
3