LMX2377U Datasheet, PDF (3/44 Pages) National Semiconductor (TI) – PLLatinum™ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications

Connection Diagrams
Thin Shrink Small Outline Package (TM)
(Top View)
Chip Scale Package (SLB)
(Top View)
20022602
Ultra Thin Chip Scale Package (SLE)
(Top View)
20022603
Pin Descriptions
Pin
Pin No.
Pin No.
Name 20-Pin UTCSP 24-Pin CSP
V_CC
20
24
V_P Main
1
2
D_o Main
2
3
GND
3
4
f_IN Main
4
5
20022696
Pin No.
20-Pin
TSSOP
1
2
3
4
5
I/O
Description
— Power supply bias for the Main PLL analog and digital circuits. V_CC
may range from 2.7V to 5.5V. Bypass capacitors should be placed
as close as possible to this pin and be connected directly to the
ground plane.
— Main PLL charge pump power supply. Must be ≥ V_CC.
O Main PLL charge pump output. The output is connected to the
external loop filter, which drives the input of the VCO.
— Ground for the Main PLL digital circuitry.
I Main PLL prescaler input. Small signal input from the VCO.
3
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