LMH0026_1 Datasheet, PDF (3/4 Pages) National Semiconductor (TI) – Replacing the CLC016 Replacing the CLC016 reclocker in many applications

The LMH0026 provides much more flexibility. The LMH0026
outputs are CML with internal 50Ω pullups to 3.3V. They may
be DC coupled to many more types of inputs, including the
LMH0001 cable driver. Typically only a far-end differential
termination (a simple resistor) is required. If the LMH0026
output common mode voltage is not compatible with the input
common mode voltage of the receiving device, the outputs
may be AC coupled. The outputs do not require pullups to
V_CC.
LOOP FILTER
The CLC016 external loop filter circuit typically consists of a
1.0 µF capacitor, an 82 pF capacitor, and a 500Ω resistor.
These components define the overall jitter transfer function
and control the acquisition performance of the PLL, and may
be changed to affect these parameters. For the LMH0026, the
external loop filter should consist of a single 56 nF capacitor
only. The LMH0026 loop filter was designed and optimized
for a 56 nF capacitor and it should not be changed.
RATE SELECTION
The CLC016 can be configured to recognize up to four differ-
ent data rates (between 40 Mbps and 400 Mbps) using ex-
ternal resistors, and can further be set to automatically detect
between these four rates or manually configured for the de-
sired rate. The LMH0026 supports a single 270 Mbps data
rate, and bypasses other data rates up to 1.5 Gbps. The
LMH0026 also requires an external 27 MHz reference clock
(crystal or suitable external reference) which is not necessary
for the CLC016, but this allows for its superior performance:
the LMH0026 has typical output jitter of 0.02 UI at 270 Mbps
(with 0.2 UI input jitter) vs. typical output jitter of 0.04 UI at 270
Mbps for the CLC016.
OTHER FEATURES
The CLC016 includes an input Carrier Detect (CD) signal to
indicate the presence of transitions at the input. In typical
CLC016 applications, CD is tied to MUTE to latch the output
when no input signal is present. The LMH0026 does not pro-
vide an input carrier detector, but it does provide a robust
LOCK DETECT signal to indicate that data is being received
and the PLL is locked. LOCK DETECT may be connected to
OUTPUT MUTE to mute the data and clock outputs when no
valid data is being received.
The LMH0026 includes advanced features not present in the
CLC016. The LMH0026 includes a BYPASS/AUTO BY-
PASS function which can be used to either force the reclocker
to output all data without reclocking it, or automatically bypass
only unsupported data rates while reclocking 270 Mbps data.
The LMH0026 also provides the option of either a second re-
clocked data output or the serial data rate clock (the CLC016
only provides the clock and has no option for a second data
output).
LMH0026 Enhancements over the
CLC016
The LMH0026 is a solid upgrade and good replacement for
the CLC016. It is designed in a newer, more advanced pro-
cess. The LMH0026 offers lower power, lower jitter, better
ESD protection, a more flexible output interface, and new
features such as a reclocker bypass and a second reclocked
data output. The LMH0026’s smaller, space-saving package
allows for more compact designs. The PCB layout is simpler
as the LMH0026 requires less PCB components overall than
the CLC016. In addition, the LMH0026’s pin compatibility with
HD-SDI and 3G-SDI equalizers offers an easy upgrade path
and allows future-proof designs.
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