DS91M125 Datasheet, PDF (3/12 Pages) National Semiconductor (TI) – 125 MHz 1:4 M-LVDS Repeater with LVDS Input

Absolute Maximum Ratings (Note 4)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
−0.3V to +4V
LVCMOS Input Voltages
M-LVDS Output Voltages
−0.3V to (V_DD + 0.3V)
−1.9V to +5.5V
LVDS Input Voltages
−0.3V to (V_DD + 0.3V)
Maximum Package Power Dissipation at +25°C
SOIC Package
2.21W
Derate SOIC Package
19.2 mW/°C above +25°C
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)
 θ_JA
 θ_JC
Maximum Junction Temperature
52°C/W
19°C/W
140°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature
(Soldering, 4 seconds)
260°C
ESD Susceptibility
HBM (Note 1)
MM (Note 2)
CDM (Note 3)
≥ 8 kV
≥ 250V
≥ 1250V
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage, V_DD
Voltage at M-LVDS Outputs
3.0 3.3 3.6 V
−1.4
+3.8 V
Voltage at LVDS Inputs
0
LVCMOS Input Voltage High V_IH 2.0
LVCMOS Input Voltage Low V_IL 0
Operating Free Air
V_DD V
V_DD V
0.8 V
Temperature T_A
−40 +25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 5, Note 6, Note 7, Note 10)
Symbol
Parameter
Conditions
Min Typ Max Units
LVCMOS DC Specifications
V_IH
High-Level Input Voltage
V_IL
Low-Level Input Voltage
I_IH
High-Level Input Current
I_IL
Low-Level Input Current
V_CL
Input Clamp Voltage
M-LVDS Driver DC Specifications
V_IH = 3.6V
V_IL = 0V
I_IN = -18 mA
2.0
GND
V_DD
V
0.8
V
-15
±1
15
μA
-15
±1
15
μA
-1.5
V
|V_AB|
ΔV_AB
Differential output voltage magnitude
Change in differential output voltage magnitude
between logic states
R_L = 50Ω, C_L = 5pF
Figures 1, 3
480
650 mV
−50 0 +50 mV
V_OS(SS)
|ΔV_OS(SS)|
Steady-state common-mode output voltage
Change in steady-state common-mode output
voltage between logic states
R_L = 50Ω, C_L = 5pF
Figures 1, 2
0.3 1.6 2.1
V
0
+50 mV
V_A(OC)
Maximum steady-state open-circuit output voltage Figure 4
0
V_B(OC)
Maximum steady-state open-circuit output voltage
0
V_P(H)
Voltage overshoot, low-to-high level output
R_L = 50Ω, C_L = 5pF, C_D = 0.5pF
Figures 6, 7 (Note 8)
2.4
V
2.4
V
1.2V_SS V
V_P(L)
I_OS
I_A
Voltage overshoot, high-to-low level output
Differential short-circuit output current
Driver output current
I_B
Driver output current
I_AB
Driver output differential current (I_A − I_B)
Figure 5 (Note 9)
V_A = 3.8V, V_B = 1.2V
V_A = 0V or 2.4V, V_B = 1.2V
V_A = −1.4V, V_B = 1.2V
V_B = 3.8V, V_A = 1.2V
V_B = 0V or 2.4V, V_A = 1.2V
V_B = −1.4V, V_A = 1.2V
V_A = V_B, −1.4V ≤ V ≤ 3.8V
−0.2V_S
S
-43
−20
−32
−20
−32
−4
V
43 mA
32 µA
+20 µA
µA
32 µA
+20 µA
µA
+4 µA
3
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