DS90CF383 Datasheet, PDF (3/9 Pages) National Semiconductor (TI) – +3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link─65 MHz

Electrical Characteristics (Continued)
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V_OD and ∆V _OD).
Note 4: V_OS previously referred as V_CM.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
LLHT
LVDS Low-to-High Transition Time (Figure 3 )
LHLT
LVDS High-to-Low Transition Time (Figure 3 )
TCIT
TxCLK IN Transition Time (Figure 4 )
TCCS
TxOUT Channel-to-Channel Skew (Figure 5 )
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 12 )
f = 65 MHz
TPPos1 Transmitter Output Pulse Position for Bit 1
TPPos2 Transmitter Output Pulse Position for Bit 2
TPPos3 Transmitter Output Pulse Position for Bit 3
TPPos4 Transmitter Output Pulse Position for Bit 4
TPPos5 Transmitter Output Pulse Position for Bit 5
TPPos6 Transmitter Output Pulse Position for Bit 6
TCIP
TxCLK IN Period (Figure 6)
TCIH
TxCLK IN High Time (Figure 6)
TCIL
TxCLK IN Low Time (Figure 6)
TSTC
TxIN Setup to TxCLK IN (Figure 6)
f = 65 MHz
THTC
TxIN Hold to TxCLK IN (Figure 6)
TCCD
TPLLS
TxCLK IN to TxCLK OUT Delay 25˚C, V_CC = 3.3V (Figure 7 )
Transmitter Phase Lock Loop Set (Figure 8 )
TPDD
Transmitter Power Down Delay (Figure 11)
Min
−0.4
1.8
4.0
6.2
8.4
10.6
12.8
15
0.35T
0.35T
2.5
0
3
Typ
0.75
0.75
250
0
2.2
4.4
6.6
8.8
11.0
13.2
T
0.5T
0.5T
Max
1.5
1.5
5
0.3
2.5
4.7
6.9
9.1
11.3
13.5
50
0.65T
0.65T
5.5
10
100
Units
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
DS100033-4
3
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