DS7834 Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Quad TRI-STATE Bus Transceivers

Switching Characteristics V_CC e 5 0V T_A e 25 C
Symbol
Parameter
Conditions
Min Typ Max Units
t_pd0
Propagation Delay to a Logic ‘‘0’’
from Input to Bus
(Figure 1)
DS7834 DS8834
10 20
ns
t_pd1
t_pd0
t_pd1
t_PHZ
t_PLZ
t_PZH
t_PZL
Propagation Delay to a Logic ‘‘1’’
from Input to Bus
Propagation Delay to a Logic ‘‘0’’
from Bus to Output
Propagation Delay to a Logic ‘‘1’’
from Bus to Output
Delay from Disable Input to High
Impedance State (from Logic ‘‘1’’ Level)
Delay from Disable Input to High
Impedance State (from Logic ‘‘0’’ Level)
Delay from Disable Input to Logic
‘‘1’’ Level (from High Impedance State)
Delay from Disable Input to Logic
‘‘0’’ Level (from High Impedance State)
(Figure 1)
DS7834 DS8834
(Figure 2)
DS7834 DS8834
(Figure 2)
DS7834 DS8834
C_L e 5 0 pF (Figures 1 and 2) Driver Only
C_L e 5 0 pF (Figures 1 and 2) Driver Only
C_L e 50 pF (Figures 1 and 2) Driver Only
C_L e 50 pF (Figures 1 and 2) Driver Only
11 30
ns
16 35
ns
18 30
ns
8
20
ns
20 35
ns
24 40
ns
19 35
ns
AC Test Circuit
TL F 5809 – 3
FIGURE 1 Driver Output Load
Switching Time Waveforms
t_pd1 and t_pd0
TL F 5809 – 4
FIGURE 2 Receiver Output Load
t_PLZ
f e 1 MHz
t_r e t_f s 10 ns (10% to 90%)
Duty Cycle e 50%
TL F 5809 – 5
3
TL F 5809 – 6
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