DS7833 Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Quad TRI-STATE Bus Transceivers

Electrical Characteristics (Notes 2 and 3) (Continued)
Symbol
Parameter
Conditions
Min Typ Max Units
RECEIVER OUTPUT (Continued)
I_OS
Output Short Circuit Current V_CC e Max (Note 4)
DS7833 DS7835 28 b40 b70 mA
DS8833 DS8835 b30
b70 mA
I_CC
Supply Current
V_CC e Max
DS7833 DS8833
84 116 mA
DS7835 DS8835
75 95 mA
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 Unless otherwise specified min max limits apply across the b55 C to a125 C temperature range for the DS7833 DS7835 and across the 0 C to a70 C
range for the DS8833 DS8835 All typicals are given for V_CC e 5 0V and T_A e 25 C
Note 3 All currents into device pins shown as positive out of device pins as negative all voltages referenced to ground unless otherwise noted All values shown
as max or min on absolute value basis
Note 4 Only one output at a time should be shorted
Switching Characteristics V_CC e 5 0V T_A e 25 C
Symbol
Parameter
Conditions
Min Typ Max Units
t_pd0
Propagation Delay to a Logic ‘‘0’’
from Input to Bus
(Figure 1)
DS7833 DS8833
DS7835 DS8835
14 30 ns
10 20 ns
t_pd1
Propagation Delay to a Logic ‘‘1’’
from Input to Bus
(Figure 1)
DS7833 DS8833
DS7835 DS8835
14 30 ns
11 30 ns
t_pd0
Propagation Delay to a Logic ‘‘0’’
from Bus to Input
(Figure 2)
DS7833 DS8833
DS7835 DS8835
24 45 ns
16 35 ns
t_pd1
Propagation Delay to a Logic ‘‘1’’
from Bus to Input
(Figure 2)
DS7833 DS8833
DS7835 DS8835
12 30 ns
18 30 ns
t_PHZ
Delay from Disable Input to High
C_L e 5 0 pF
Driver
Impedance State (from Logic ‘‘1’’ Level) (Figures 1 and 2 ) _Receiver
8 0 20 ns
6 0 15 ns
t_PLZ
Delay from Disable Input to High
C_L e 5 0 pF
Driver
Impedance State (from Logic ‘‘0’’ Level) (Figures 1 and 2 ) _Receiver
20 35 ns
13 25 ns
t_PZH
Delay from Disable Input to Logic
‘‘1’’ Level (from High Impedance State)
C_L e 5 0 pF
Driver
(Figures 1 and 2 ) _Receiver
24 40 ns
16 35 ns
t_PZL
Delay from Disable Input to Logic
C_L e 5 0 pF
Driver
‘‘0’’ Level (from High Impedance State) (Figures 1 and 2 ) _{Receiver DS7833 DS8833}
19 35 ns
15 30 ns
Receiver DS7835 DS8835
33 50 ns
AC Test Circuits
TL F 5808 – 3
FIGURE 1 Driver Output Load
3
TL F 5808 – 4
FIGURE 2 Receiver Output Load
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