DS7831_99 Datasheet, PDF (3/11 Pages) National Semiconductor (TI) – Dual TRI-STATE Line Driver

Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature Range
−65˚C to +150˚C
Lead Temperature (Soldering, 4 sec.)
260˚C
Maximum Power Dissipation (Note 1) at 25˚C
Cavity Package
1433 mW
Molded Package
1362 mW
Operating Conditions
Min
Max
Units
Supply Voltage (V_CC)
DS7831
4.5
5.5
V
DS8831/DS8832
4.75
5.25
V
Temperature (T_A)
DS7831
−55
+125
˚C
DS8832
0
+70
˚C
Note 1: Derate cavity package 9.6 mW/˚C above 25˚C; derate molded pack-
age 10.9 mW/˚C above 25˚C.
Electrical Characteristics (Notes 3, 4)
Symbol
V_IH
V_IL
V_OH
Parameter
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
V_OL
Logical “0” Output Voltage
I_IH
Logical “1” Input Current
I_IL
I_OD
I_SC
I_CC
V_CLI
V_CLO
Logical “0” Input Current
Output Disable Current
Output Short Circuit Current
Supply Current
Input Diode Clamp Voltage
Output Diode Clamp
Voltage
Conditions
V_CC = Min
V_CC = Min
DS7831
I_O = −40 mA
V_CC = Min
I_O = −2 mA
DS8832
I_O = −40 mA
I_O = −5.2 mA
DS7831
I_O = 40 mA
V_CC = Min
I_O = 32 mA
DS8832
I_O = 40 mA
I_O = 32 mA
V_CC = Max
DS7831, V_IN = 5.5V
DS8832, V_IN = 2.4V
V_CC = Max, V_IN = 0.4V
V_CC = Max, V_O = 2.4V or 0.4V
V_CC = Max, (Note 5)
V_CC = Max in TRI-STATE
V_CC = 5.0V, T_A = 25˚C, I_IN = −12 mA
V_CC = 5.0V,
I_OUT = −12 mA DS7831
T_A = 25˚C
DS8832
I_OUT = 12 mA
DS7831
Min Typ
2.0
1.8 2.3
2.4 2.7
1.8 2.5
2.4 2.9
0.29
0.29
−1.0
−40
−40 −100
65
Max
0.8
0.50
0.40
0.50
0.40
1
40
−1.6
40
−120
90
−1.5
−1.5
Units
V
V
V
V
V
V
V
V
V
V
mA
µA
mA
µA
mA
mA
V
V
V_CC + 1.5 V
Switching Characteristics
T_A = 25˚C, V_CC = 5V, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_pd0
Propagation Delay to a Logical “0”
from Inputs A1, A2, B1, B2
13
25
ns
Differential Single-ended Mode
Control to Outputs
t_pd1
Propagation Delay to a Logical “1”
from Inputs A1, A2, B1, B2
13
25
ns
Differential Single-ended Mode
Control to Outputs
t_1H
Delay from Disable Inputs to High
Impedance State (from Logical “1”
(See Figure 4 and Figure 5 )
6
12
ns
Level)
t_0H
Delay from Disable Inputs to High
Impedance State (from Logical “0” Level)
14
22
ns
3
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