DS7831 Datasheet, PDF (3/8 Pages) National Semiconductor (TI) – Dual TRI-STATE Line Driver

Switching Characteristics T_A 25 C V_CC 5V unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_pd0
Propagation Delay to a Logical ‘‘0’’
from Inputs A1 A2 B1 B2
Differential Single-ended Mode
Control to Outputs
13
25
ns
t_pd1
Propagation Delay to a Logical ‘‘1’’
from Inputs A1 A2 B1 B2
Differential Single-ended Mode
Control to Outputs
13
25
ns
t_1H
Delay from Disable Inputs to High
Impedance State (from Logical ‘‘1’’
Level)
(See Figures 4 and 5 )
6
12
ns
t_0H
Delay from Disable Inputs to High
Impedance State (from Logical ‘‘0’’
Level)
14
22
ns
t_H1
Propagation Delay from Disable Inputs
to Logical ‘‘1’’ Level (from High
Impedance State)
14
22
ns
t_H0
Propagation Delay from Disable Inputs
to Logical ‘‘0’’ Level (from High
Impedance State)
18
27
ns
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 Unless otherwise specified min max limits apply across the 55 C to a125 C temperature range for the DS7831 and DS7832 and across the 0 C to
a70 C range for the DS8831 and DS8832 All typical values are for T_A 25 C and V_CC 5V
Note 3 All currents into device pins shown as positive out of device pins as negative all voltage referenced to ground unless otherwise noted All values shown as
max or min on absolute value basis
Note 4 Applies for T_A 125 C only Only one output should be shorted at a time
Mode of Operation
To operate as a quad single-ended line driver apply logical
‘‘0’’s to the output disable pins (to keep the outputs in the
normal low impedance mode) and apply logical ‘‘0’’s to both
Differential Single-ended Mode Control inputs All four
channels will then operate independently and no signal in-
version will occur between inputs and outputs
To operate as a dual differential line driver apply logical
‘‘0’’s to the Output Disable pins and apply at least one logi-
cal ‘‘1’’ to the Differential Single-ended Mode Control in-
puts
The inputs to the A channels should be connected together
and the inputs to the B channels should be connected to-
gether
In this mode the signals applied to the resulting inputs will
pass non-inverted on the A₂ and B₂ outputs and inverted on
the A₁ and B₁ outputs
When operating in a bus-organized system with outputs tied
directly to outputs of other DS7831 DS8831’s DS7832
DS8832’s (Figure 1) all devices except one must be placed
in the ‘‘high impedance’’ state This is accomplished by en-
suring that a logical ‘‘1’’ is applied to at least one of the
Output Disable pins of each device which is to be in the
‘‘high impedance’’ state A NOR gate was purposely chosen
for this function since it is possible with only two DM5442
DM7442 BCD-to-decimal decoders to decode as many as
100 DS7831 DS8831’s DS7832 DS8832’s (Figure 2)
The unique device whose Disable inputs receive two logical
‘‘0’’ levels assumes the normal low impedance output state
providing good capacitive drive capability and waveform in-
tegrity especially during the transition from the logical ‘‘0’’ to
logical ’’1’’ state The other outputs in the high impedance
state take only a small amount of leakage current from the
low impedance outputs Since the logical ‘‘1’’ output current
from the selected device is 100 times that of a conventional
Series 54 74 device (40 mA vs 400 mA) the output is easily
able to supply that leakage current for several hundred oth-
er DS7831 DS8831’s DS7832 DS8832’s and still have
available drive for the bus line (Figure 3)
3
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