DS75162A Datasheet, PDF (3/10 Pages) National Semiconductor (TI) – IEEE-488 GPIB Transceivers

Switching Characteristics V_CC e 5 0V g5% T_A e 0 C to 70 C (Note 1)
Symbol
Parameter
From
DS75160A
To Conditions
DS75161A
DS75162A
Units
Min Typ Max Min Typ Max Min Typ Max
t_PLH
Propagation Delay Time
Low to High Level Output _{Terminal Bus}
t_PHL
Propagation Delay Time
High to Low Level Output
V_L e 2 3V
R_L e 38 3X
C_L e 30 pF
Figure 1
10 20
14 20
10 20
14 20
10 20 ns
14 20 ns
t_PLH
Propagation Delay Time
Low to High Level Output
Bus
t_PHL
Propagation Delay Time
High to Low Level Output
V_L e 5 0V
Terminal ^{RL e 240X}
C_L e 30 pF
Figure 2
14 20
10 20
14 20
10 20
14 20 ns
10 20 ns
t_PZH
t_PHZ
Output Enable Time
to High Level
Output Disable Time
From High Level
TE DC
or SC
V_I e 3 0V
V_L e 0V
R_L e 480X
C_L e 15 pF
Figure 1
19 32
15 22
23 40
15 25
23 40 ns
15 25 ns
t_PZL
Output Enable Time
to Low Level
t_PLZ
Output Disable Time
From Low Level
(Note 2) ^Bus
(Note 3)
V_I e 0V
V_L e 2 3V
R_L e 38 3X
C_L e 15 pF
Figure 1
24 35
17 25
28 48
17 27
28 48 ns
17 27 ns
t_PZH
t_PHZ
Output Enable Time
to High Level
Output Disable Time
From High Level
TE DC
or SC
V_I e 3 0V
V_L e 0V
R_L e 3 kX
C_L e 15 pF
Terminal _{Figure 1}
17 33
15 25
18 40
22 33
18 40 ns
22 33 ns
t_PZL
Output Enable Time
to Low Level
t_PLZ
Output Disable Time
From Low Level
(Note 2)
(Note 3)
V_I e 0V
V_L e 5V
R_L e 280X
C_L e 15 pF
Figure 1
25 39
15 27
28 52
20 35
28 52 ns
20 35 ns
t_PZH
Output Pull-Up Enable
V_I e 3V
10 17
NA
t_PHZ
Time (DS75160A Only)
Output Pull-UP Disable
Time (DS75160A Only)
PE
Bus
(Note 2)
V_L e 0V
R_L e 480X
C_L e 15 pF
10 15
NA
Figure 1
NA
ns
NA
ns
Note 1 Typical values are for V_CC e 5 0V and T_A e 25 C and are meant for reference only
Note 2 Refer to Functional Truth Tables for control input definition
Note 3 Test configuration should be connected to only one transceiver at a time due to the high current stress caused by the V_I voltage source when the output
connected to that input becomes active
Switching Load Configurations
V_C logic high e 3 0V
V_C logic low e 0V
C_L includes jig and probe capacitance
FIGURE 1
TL F 5804 – 8
3
V_C logic high e 3 0V
V_C logic low e 0V
C_L includes jig and probe capacitance
FIGURE 2
TL F 5804 – 9
http www national com