DS15MB200 Datasheet, PDF (3/10 Pages) National Semiconductor (TI) – Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

Pin Descriptions (Continued)
Pin
Name
POWER
V_DD
GND
LLP Pin
I/O, Type
Number
Description
2, 6, 12,
37, 43,
46, 48
3, 47
(Note 2)
I, Power V_DD = 3.3V ±0.3V.
I, Power
Ground reference for LVDS and CMOS circuitry.
For the LLP package, the DAP is used as the primary GND connection to the device. The
DAP is the exposed metal contact at the bottom of the LLP-48 package. It should be
connected to the ground plane with at least 4 vias for optimal AC and thermal performance.
Note 1: For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the applications section of this datasheet (planned).
Note 2: Note that the DAP on the backside of the LLP package is the primary GND connection for the device when using the LLP package.
Note 3: The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS15MB200 device have been optimized for
point-to-point backplane and cable applications.
Connection Diagrams
LLP Top View
DAP = GND
20157302
20157303
Directional Signal Paths Top View
(Refer to pin names for signal polarity)
3
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