DP83251 Datasheet, PDF (3/96 Pages) National Semiconductor (TI) – PLAYER Device (FDDI Physical Layer Controller)

1 0 FDDI Chip Set Overview
National Semiconductor’s FDDI chip set consists of five
components as shown in Figure 1-1 For more information
on the other devices of the chip set consult the appropriate
datasheets and application notes
DP83231 CRD^TM Device
Clock Recovery Device
The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream
Features
 PHY Layer loopback test
 Crystal controlled
 Clock locks in less than 85 ms
DP83241 CDD^TM Device
Clock Distribution Device
From a 12 5 MHz reference the Clock Distribution Device
synthesizes the 125 MHz 25 MHz and 12 5 MHz clocks
required by the BSI BMAC and PLAYER devices
DP83251 55 PLAYER^TM Device
Physical Layer Controller
The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9 5 Stan-
dard
Features
 4B 5B encoders and decoders
 Framing logic
 Elasticity Buffer Repeat Filter and Smoother
 Line state detector generator
 Link error detector
 Configuration switch
 Full duplex operation
 Separate management port that is used to configure and
control their operation
In addition the DP83255 contains an additional
PHY Data request and PHY Data indicate port required
for concentrators and dual attach stations
DP83261 BMAC^TM Device
Media Access Controller
The BMAC device implements the Timed Token Media Ac-
cess Control protocol defined by the ANSI FDDI X3T9 5
MAC Standard
Features
 All of the standard defined ring service options
 Full duplex operation with through parity
Supports all FDDI Ring Scheduling Classes (Synchro-
nous Asynchronous etc )
 Supports Individual Group Short Long and External
Addressing
 Generates Beacon Claim and Void frames internally
 Extensive ring and station statistic gathering
 Extensions for MAC level bridging
 Separate management port that is used to configure and
control their operation
 Multi-frame streaming interface
DP83265 BSI^TM Device
System Interface
The BSI device implements the interface between the
BMAC device and a host system
Features
 32-bit wide Address Data path with byte parity
 Programmable transfer burst sizes of 4 or 8 32-bit words
 Interfaces to low cost DRAMs or directly to system bus
 Provides 2 Output and 3 Input Channels
 Supports Header Info splitting
 Efficient data structures
 Programmable Big or Little Endian alignment
 Full duplex data path allows transmission to self
 Confirmation status batching services
 Receive frame filtering services
 Operates from 12 5 MHz to 25 MHz synchronously with
the host system
3