DM54LS107A Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) (Continued)
Symbol
I_IH
I_IL
I_OS
I_CC
Parameter
High Level Input
Current
Low Level Input
Current
Short Circuit
Output Current
Supply Current
Conditions
V_CC e Max
V_I e 2 7V
JK
Clear
Clock
V_CC e Max
V_I e 0 4V
JK
Clear
Clock
V_CC e Max
(Note 2)
DM54
DM74
V_CC e Max (Note 3)
Min
b20
b20
Typ
(Note 1)
4
Max
20
60
80
b0 4
b0 8
b0 8
b100
b100
6
Units
mA
mA
mA
mA
Switching Characteristics at V_CC e 5V and T_A e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
R_L e 2 kX
C_L e 15 pF
C_L e 50 pF
Min
Max
Min
Max
Units
f_MAX
Maximum Clock
Frequency
30
25
MHz
t_PLH
Propagation Delay Time
Preset
Low to High Level Output
to Q
20
24
ns
t_PHL
Propagation Delay Time
Preset
High to Low Level Output
to Q
20
28
ns
t_PLH
Propagation Delay Time
Low to High Level Output
Clear
to Q
20
24
ns
t_PHL
Propagation Delay Time
High to Low Level Output
Clear
to Q
20
28
ns
t_PLH
Propagation Delay Time
Clock to
Low to High Level Output
Q or Q
20
24
ns
t_PHL
Propagation Delay Time
Clock to
High to Low Level Output
Q or Q
20
28
ns
Note 1 All typicals are at V_CC e 5V T_A e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second For devices with feedback from the outputs where
shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V_O e 2 25V and 2 125V for DM54 and
DM74 series respectively with the minimum and maximum limits reduced by one half from their stated values This is very useful when using automatic test
equipment
Note 3 With all inputs open I_CC is measured with the Q and Q outputs high in turn At the time of measurement the clock is grounded
3