COP410C Datasheet, PDF (3/20 Pages) National Semiconductor (TI) – Single-Chip CMOS Microcontrollers

COP410C COP411C
DC Electrical Characteristics (Continued)
Parameter
Conditions
Min
Max
Units
Allowable Loading on CKO
(as HALT I O pin)
100
pF
Current Needed to
Override HALT³
To Continue
To Halt
V_CC e 4 5V V_IN e 0 2 V_CC
V_CC e 4 5V V_IN e 0 7 V_CC
06
mA
16
mA
TRI-STATE or Open Drain
Leakage Current
b2
a2
mA
Note 1 Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI CKO open and all other pins pulled up to V_CC with 5k
resistors See current drain equation on page 13
Note 2 The Halt mode will stop CKI from oscillating in the RC and crystal configurations
Note 3 When forcing HALT current is only needed for a short time (approximately 200 ns) to flip the HALT flip-flop
Note 4 SO output sink current must be limited to keep V_OL less than 0 2 V_CC when part is running in order to prevent entering test mode
Note 5 Voltage change must be less than 0 5V in a 1 ms period
Note 6 This parameter is only sampled and not 100% tested
Note 7 Variation due to the device included
COP410C COP411C
AC Electrical Characteristics 0 C ^s T_A ^s 70 C unless otherwise specified
Parameter
Conditions
Min
Max
Units
Instruction Cycle Time (t_c)
Operating CKI d4 mode
Frequency d8 mode
d16 mode
d4 mode
d8 mode
d16 mode
V_CC ^t 4 5V
4 5V ^l V_CC ^t 2 4V
( ^{VCC t 4 5V}
( ^{4 5V l VCC t 2 4V}
4
DC
ms
16
DC
ms
DC
10
MHz
DC
20
MHz
DC
40
MHz
DC
250
kHz
DC
500
kHz
DC
10
MHz
Instruction Cycle Time
RC Oscillator⁷
Duty Cycle⁶
Rise Time⁶
Fall Time⁶
Inputs (See Figure 3 )
t_SETUP
t_HOLD
Output Propagation
Delay
t_PD1 t_PD0
t_PD1 t_PD0
R e 30k g 5% V_CC e 5V
C e 82 pF g 5% (d4 Mode)
f_I e 4 MHz
f_I e 4 MHz External Clock
f_I e 4 MHz External Clock
8
16
ms
40
60
%
60
ns
40
ns
G Inputs
tc 4a0 7
ms
( ^{SI Input}
All Others
V_CC ^t 4 5V
03
17
ms
ms
V_CC ^t 4 5V
V_CC ^t 2 4V
0 25
ms
10
ms
V_OUT e 1 5V C_L e 100 pF R_L e 5k
V_CC ^s 4 5V
V_CC ^s 2 4V
10
ms
40
ms
3