CD4512BM Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – 8-Channel Buffered Data Selector

DC Electrical Characteristics CD4512BC (Note 2) (Continued)
Symbol
V_IH
I_OL
I_OH
I_IN
I_OZ
Parameter
High Level
Input Voltage
Low Level Output
Current
(Note 3)
High Level Output
Current
(Note 3)
Input Current
TRI-STATE
Output Current
Conditions
V_DD e 5V V_O e 4 5V
V_DD e 10V V_O e 9 0V
V_DD e 15V V_O e 13 5V
V_DD e 5V V_O e 0 4V
V_DD e 10V V_O e 0 5V
V_DD e 15V V_O e 1 5V
V_DD e 5V V_O e 4 6V
V_DD e 10V V_O e 9 5
V_DD e 15V V_O e 13 5V
V_DD e 15V V_IN e 0V
V_DD e 15V V_IN e 15V
V_DD e 15V V_O e 0V
V_DD e 15V V_O e 15V
b40 C
Min Max
35
70
11 0
0 52
13
36
b0 2
b0 5
b1 4
b0 3
03
g1 0
Min
35
70
11 0
0 44
11
34
b0 16
b0 4
b1 2
a25 C
Typ
2 75
5 50
8 25
0 78
20
78
b10^b5
10^b5
g10^b5
Max
b0 3
03
g1 0
a85 C
Min Max
35
70
11 0
0 36
09
24
b0 12
b0 3
b1 0
b1 0
10
g7 5
Units
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
AC Electrical Characteristics T_A e 25 C t_r e t_f e 20 ns C_L e 50 pF
Symbol
Parameter
Conditions
CD4512BM
Min Typ Max
CD4512BC
Min Typ Max
Units
t_PHL
t_PLH
t_THL t_TLH
t_PHZ t_PLZ
t_PZH t_PZL
C_IN
C_OUT
Propagation Delay
High-to-Low Level
Propagation Delay
Low-to-High Level
Transition Time
Propagation Delay into
TRI-STATE from Logic Level
Propagation Delay to Logic
Level from TRI-STATE
Input Capacitance
TRI-STATE Output
Capacitance
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
V_DD e 5V
V_DD e 10V
V_DD e 15V
(Note 4)
(Note 4)
225
500
75
175
57
130
225
500
75
175
57
130
70
200
35
100
25
80
50
125
25
75
19
60
50
125
25
75
19
60
75
15
75
15
225 750
ns
75
200
ns
57
150
ns
225 750
ns
75
200
ns
57
150
ns
70
200
ns
35
100
ns
25
80
ns
50
125
ns
25
75
ns
19
60
ns
50
125
ns
25
75
ns
19
60
ns
75
15
pF
75
15
pF
C_PD
Power Dissipation Capacity
(Note 5)
150
150
pF
AC Parameters are guaranteed by DC correlated testing
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation
Note 2 V_SS e 0V unless otherwise specified
Note 3 I_OH and I_OL are tested one output at a time
Note 4 Capacitance guaranteed by periodic testing
Note 5 C_PD determines the no load AC power of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90
3