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CD4043BM Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – Quad TRI-STATE NOR(NAND) R/S Latches
DC Electrical Characteristics CD4043BC CD4044BC (Continued)
Symbol
VIL
VIH
IOL
IOH
IIN
Parameter
Low Level
Input Voltage
High Level
Input Voltage
Low Level
Output Current
(Note 3)
High Level
Output Current
(Note 3)
Input Current
Conditions
lIOl s 1 mA
VDD e 5 0V VO e 0 5V or 4 5V
VDD e 10V VO e 1 0V or 9 0V
VDD e 15V VO e 1 5V or 13 5V
lIOl s 1 mA
VDD e 5 0V VO e 0 5V or 4 5V
VDD e 5 0V VO e 1 0V or 9 0V
VDD e 15V VO e 1 5V or 13 5V
VIL e 0V VIH e VDD
VDD e 5 0V VO e 0 4V
VDD e 10V VO e 0 5V
VDD e 15V VO e 1 5V
VIL e 0V VIH e VDD
VDD e 5 0V VO e 4 6V
VDD e 10V VO e 9 5V
VDD e 15V VO e 13 5V
VDD e 15V VIN e 0V
VDD e 15V VIN e 15V
b40 C
Min Max
15
30
40
35
70
11
0 52
13
36
b0 52
b1 3
b3 6
b0 3
03
a25 C
Min Typ
2 25
45
6 75
35
70
11
0 44 0 88
11
22
30
60
b0 44
b1 1
b3 0
b0 32
b0 8
b2 4
b0 3
03
Max
15
30
40
a85 C
Min Max
15
30
40
35
70
11
0 36
09
24
b0 36
b0 9
b2 4
b1 0
10
Units
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
AC Electrical Characteristics
TA e 25 C CL e 50 pF RL e 200k input tr e tf e 20 ns unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tPLH tPHL
Propagation Delay S or R to Q
VDD e 5 0V
VDD e 10V
VDD e 15V
175
350
ns
75
175
ns
60
120
ns
tPZH tPHZ
Propagation Delay Enable to Q (High)
VDD e 5 0V
VDD e 10V
VDD e 15V
115
230
ns
55
110
ns
40
80
ns
tPZL tPLZ
Propagation Delay Enable to Q (Low)
VDD e 5 0V
VDD e 10V
VDD e 15V
100
200
ns
50
100
ns
40
80
ns
tTHL tTLH
Transition Time
VDD e 5 0V
VDD e 10V
VDD e 15V
100
200
ns
50
100
ns
40
80
ns
tWO
Minimum SET or RESET Pulse Width
VDD e 5 0V
VDD e 10V
VDD e 15V
80
160
ns
40
80
ns
20
40
ns
CIN
Input Capacitance
50
75
pF
AC Parameters are guaranteed by DC correlated testing
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices
should be operated at these limits The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation
Note 2 VSS e 0V unless otherwise specified
Note 3 IOH and IOL are tested one output at a time
3