CD40161BM Datasheet, PDF (3/8 Pages) National Semiconductor (TI) – Decade Counter with Asynchronous Clear

DC Electrical Characteristics CD40160BC CD40161BC CD40162BC CD40163BC (Note 2) (Continued)
Symbol
V_IH
I_OL
I_OH
I_IN
Parameter
High Level Input
Voltage
Low Level Output
Current (Note 3)
High Level Output
Current (Note 3)
Input Current
Conditions
V_DDe5V V_Oe0 5V or 4 5V
V_DDe10V V_Oe1V or 9V
V_DDe15V V_Oe1 5V or 13 5V
V_DDe5V V_Oe0 4V
V_DDe10V V_Oe0 5V
V_DDe15V V_Oe1 5V
V_DDe5V V_Oe4 6V
V_DDe10V V_Oe9 5V
V_DDe15V V_Oe13 5V
V_DDe15V V_INe0V
V_DDe15V V_INe15V
b40 C
Min Max
35
70
11 0
0 52
13
36
b0 52
b1 3
b3 6
b0 30
0 30
Min
35
70
11 0
0 44
11
30
b0 44
b1 1
b3 0
Limits
a25 C
Typ
0 88
2 25
88
b0 88
b2 25
b8 8
b10^b5
10^b5
Max
b0 30
0 30
a85 C
Min Max
35
70
11 0
0 36
09
24
b0 36
b0 9
b2 4
b1 0
10
Units
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
AC Electrical Characteristics T_A e 25 C C_L e 50 pF R_L e 200k unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t_PHL or t_PLH
Propagation Delay Time from
Clock to Q
V_DD e 5V
V_DD e 10V
V_DD e 15V
250
400
ns
100
160
ns
80
130
ns
t_PHL or t_PLH
Propagation Delay Time from
Clock to Carry Out
V_DD e 5V
V_DD e 10V
V_DD e 15V
290
450
ns
120
190
ns
100
160
ns
t_PHL or t_PLH
Propagation Delay Time from T
Enable to Carry Out
V_DD e 5V
V_DD e 10V
V_DD e 15V
180
290
ns
70
130
ns
60
110
ns
t_PHL
Propagation Time from Clear to Q
V_DD e 5V
(CD40160B CD40161B Only)
V_DD e 10V
V_DD e 15V
190
300
ns
80
150
ns
70
120
ns
t_SU
Minimum Time Prior to Clock that
V_DD e 5V
120
ns
Data or Load must be Present
V_DD e 10V
30
ns
V_DD e 15V
25
ns
t_SU
Minimum Time Prior to Clock that
V_DD e 5V
Enable P or T must be Present
V_DD e 10V
V_DD e 15V
170
280
ns
70
120
ns
60
100
ns
t_SU
Minimum Time Prior to Clock that
V_DD e 5V
Clear must be Present (CD40162B
V_DD e 10V
CD40163B Only)
V_DD e 15V
120
190
ns
50
80
ns
40
70
ns
t_WL or t_WH
Maximum Clock Pulse Width
V_DD e 5V
V_DD e 10V
V_DD e 15V
125
250
ns
45
90
ns
35
70
ns
t_RCL or t_FCL
Maximum Clock Rise or Fall Time
V_DD e 5V
V_DD e 10V
V_DD e 15V
15
ms
50
ms
50
ms
f_CL
Maximum Clock Frequency
V_DD e 5V
2
4
V_DD e 10V
55
11
V_DD e 15V
7
14
MHz
MHz
MHz
t_THL or t_TLH
Transition Time
All Outputs
V_DD e 5V
V_DD e 10V
V_DD e 15V
100
200
ns
50
100
ns
40
80
ns
C_IN
Average Input Capacitance
Any Input
50
75
pF
C_PD
Power Dissipation Capacity
(Note 4)
95
pF
AC Parameters are guaranteed by DC correlated testing
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices
should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation
Note 2 V_SS e 0V unless otherwise specified
Note 3 I_OH and I_OL are tested one output at a time
Note 4 C_PD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note
AN-90
3