ADC14V155 Datasheet, PDF (3/22 Pages) Texas Instruments – 1.1 GHz Bandwidth A/D Converter with LVDS Outputs

Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
3
Symbol
V_IN−
4
V_IN+
Equivalent Circuit
Description
Differential analog input pins. The differential full-scale input signal
level is two times the reference voltage with each input pin signal
centered on a common mode voltage, V_CM.
43
V_RP
45
V_RM
44
V_RN
46
V_REF
8
CLK_SEL/DF
7
PD/Sleep
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close
to the pin to minimize stray inductance. A 0.1 µF capacitor should
be placed between V_RP and V_RN as close to the pins as possible,
and a 10 µF capacitor should be placed in parallel.
V_RP and V_RN should not be loaded. V_RM may be loaded to 1mA for
use as a temperature stable 1.5V reference.
It is recommended to use V_RM to provide the common mode
voltage, V_CM, for the differential analog inputs, V_IN+ and V_IN−.
This pin can be used as either the +1.0V internal reference voltage
output (internal reference operation) or as the external reference
voltage input (external reference operation).
To use the internal reference, V_REF should be decoupled to AGND
with a 0.1 µF, low equivalent series inductance (ESL) capacitor. In
this mode, V_REF defaults as the output for the internal 1.0V
reference.
To use an external reference, overdrive this pin with a low noise
external reference voltage. The input impedance looking into this
pin is 9kΩ. Therefore, to overdrive this pin, the output impedance
of the external reference source should be << 9kΩ.
This pin should not be used to source or sink current.
The full scale differential input voltage range is 2 * V_REF.
This is a four-state pin controlling the input clock mode and output
data format.
CLK_SEL/DF = V_A, CLK+ and CLK− are configured as a
differential clock input. The output data format is 2's complement.
CLK_SEL/DF = (2/3)*V_A, CLK+ and CLK− are configured as a
differential clock input. The output data format is offset binary.
CLK_SEL/DF = (1/3)*V_A, CLK+ is configured as a single-ended
clock input and CLK− should be tied to AGND. The output data
format is 2's complement.
CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock
input and CLK− should be tied to AGND. The output data format is
offset binary.
This is a three-state input controlling Power Down and Sleep
modes.
PD = V_A, Power Down is enabled. In the Power Down state only
the reference voltage circuitry remains active and power dissipation
is reduced.
PD = V_A/2, Sleep mode is enabled. Sleep mode is similar to Power
Down mode - it consumes more power but has a faster recovery
time.
PD = AGND, Normal operation.
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