ADC10DV200 Datasheet, PDF (3/24 Pages) National Semiconductor (TI) – Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs

Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
13
3
14
2
Symbol
V_INA+
V_INB+
V_INA-
V_INB-
Equivalent Circuit
Description
Differential analog input pins. The differential full-scale input
signal level is 1.5V_P-P with each input pin signal centered on
a common mode voltage, V_CM.
10
V_RPA
6
V_RPB
11
V_RMA
5
V_RMB
9
V_RNA
7
V_RNB
17
V_REF
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very
close to the pin to minimize stray inductance. An 0201 size 0.1
µF capacitor should be placed between V_RP and V_RN as close
to the pins as possible.
V_RP and V_RN should not be loaded. V_RM may be loaded to 1mA
for use as a temperature stable 0.9V reference.
It is recommended to use V_RM to provide the common mode
voltage, V_CM for the differential analog inputs.
Reference Voltage select pin and external reference input.
The relationship between the voltage on the pin and the
reference voltage is as follows:
1.4V ≤ V_REF ≤ VA
The internal 0.75V reference is
used.
0.2V ≤ V_REF ≤ 1.4V
The external reference voltage is
used.
Note: When using an external
reference, be sure to bypass with
a 0.1µF capacitor to AGND as
close to the pin as possible.
AGND ≤ V_REF ≤ 0.2V
The internal 0.5V reference is
used.
19
R_EXT
Programming resistor for analog bias current. Nominally a
3.3kΩ to AGND for 200MSPS, or tie to V_A to use the internal
frequency scaling current.
20
DF/DCS
Data Format/Duty Cycle Correction selection pin.
(see Table 1)
3
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