93L38 Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – 8-Bit Multiple Port Register

Switching Characteristics V_CC e a5 0V T_A e a25 C (See Section 1 for Test Waveforms and Output Load
Symbol
Parameter
C_L e 15 pF
Min
Max
Units
t_PLH
t_PHL
t_PLH
t_PHL
t_PLH
t_PHL
Propagation Delay
B_n or C_n or Z_n
Propagation Delay
D_A to Z_n
Propagation Delay
CP to Z_n
68
95
ns
70
ns
92
65
ns
57
Functional Description
The 93L38 8-bit multiple port register can be considered a
1-bit slice of eight high speed working registers Data can be
written into any one and read from any two of the eight
locations simultaneously Master slave operation eliminates
all race problems associated with simultaneous read write
activity from the same location When the clock input (CP) is
LOW data applied to the data input line (D_A) enters the
selected master This selection is accomplished by coding
the three write input select lines (A0–A2) appropriately
Data is stored synchronously with the rising edge of the
clock pulse
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0 – B2 and
C0 – C2) The information enters the slave while the clock is
HIGH and is stored while the clock is LOW If Slave Enable
is LOW (SLE) the slave latches are continuously enabled
The signals are available on the output pins (Z_B and Z_C)
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously The data
flows into the device is demultiplexed according to the state
of the write address lines and is clocked into the selected
latch The eight latches function as masters and store the
input data The two output latches are slaves and hold the
data during the read operation The state of each slave is
determined by the state of the master selected by its associ-
ated set of read address inputs
The method of parallel expansion is shown in Figure A One
93L38 is needed for each bit of the required word length
The read and write input lines should be connected in com-
mon on all of the devices This register configuration pro-
vides two words of n-bits each at one time where n devices
are connected in parallel
FIGURE A Parallel Expansion
3
TL F 10202 – 4